Packet Features are enhanced packet management controls (Mark, Restore and Release functions) that facilitate packet retransmission or receive packet discard.

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Presentation transcript:

Packet Features are enhanced packet management controls (Mark, Restore and Release functions) that facilitate packet retransmission or receive packet discard functionality. Packet FIFO designs utilize a single synchronous clock domain for the input and output sides. Packet FIFO Q & A

Four Configurations of PLB IPIF SW reset/ MIR Packet FIFOs Packet Features WrFIFO DRE support Interrupt Service Burst Service Master Service SESR/ SEAR Simple DMA DMA/ Scatter Gather Wishful Config Reason- abel Config Bare- bone Config_ 1 Bare- bone Config_ 2

Wishful Configuration Device utilization summary: Selected Device : 2vp100ff Number of Slices: 2147 out of % Number of Slice Flip Flops: 2092 out of % Number of 4 input LUTs: 3844 out of % Number of bonded IOBs: 758 out of % Number of BRAMs: 4 out of 444 0% Number of GCLKs: 1 out of 16 6% Timing Summary: Speed Grade: -6 Minimum period: 9.041ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 7.528ns Maximum output required time after clock: 7.122ns Maximum combinational path delay: 6.753ns

Reasonable Configuration Device utilization summary: Selected Device : 2vp100ff Number of Slices: 1797 out of % Number of Slice Flip Flops: 1806 out of % Number of 4 input LUTs: 3261 out of % Number of bonded IOBs: 752 out of % Number of BRAMs: 4 out of 444 0% Number of GCLKs: 1 out of 16 6% Timing Summary: Speed Grade: -6 Minimum period: 8.645ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 7.519ns Maximum output required time after clock: 7.257ns Maximum combinational path delay: 6.489ns

Barebone 1 Configuration Device utilization summary: Selected Device : 2vp100ff Number of Slices: 375 out of % Number of Slice Flip Flops: 592 out of % Number of 4 input LUTs: 543 out of % Number of bonded IOBs: 541 out of % Number of BRAMs: 4 out of 444 0% Number of GCLKs: 1 out of 16 6% Timing Summary: Speed Grade: -6 Minimum period: 6.385ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 6.666ns Maximum output required time after clock: 6.915ns Maximum combinational path delay: 6.208ns

Barebone 2 Configuration Device utilization summary: Selected Device : 2vp100ff Number of Slices: 338 out of % Number of Slice Flip Flops: 546 out of % Number of 4 input LUTs: 465 out of % Number of bonded IOBs: 537 out of % Number of BRAMs: 4 out of 444 0% Number of GCLKs: 1 out of 16 6% Timing Summary: Speed Grade: -6 Minimum period: 6.359ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 6.467ns Maximum output required time after clock: 6.915ns Maximum combinational path delay: 6.184ns