CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005 Some slides and/or pictures in the following are adapted from: slides ©2008 UCB 18

What about overflow? Highest adder –C in, but no C out  A,B both > 0, overflow! –C out, but no C in  A,B both < 0, overflow! –C in, C out  no overflow! –no C in, no C out  no overflow! What op?

What are the values of the control lines and what operations do they correspond to?

Speed of Ripple Carry The carry propagates through every 1-bit box: each 1-bit box sequentially implements AND and OR – total delay is the time to go through 64 gates!

Faster Addition: Carry Lookahead Key to speeding up addition is determining the carry into the high-order bits sooner –We’ve already seen that any logic equation can be expressed as the sum of products – so it should be possible to compute the result by going through only 2 gates! (IN CLASS)

Faster Addition: Carry Lookahead Caveat: need many parallel gates and each gate may have a very large number of inputs – it is difficult to efficiently build such large gates, so we find a compromise: – moderate number of gates – moderate number of inputs to each gate – moderate number of sequential gates traversed

Processor Computer Control Datapath Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) Five Components of a Computer

Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision-making) –Datapath: portion of the processor which contains hardware necessary to perform operations required by the processor (the brawn) –Control: portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain) The CPU

Our implementation of the MIPS is simplified –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq, j Generic implementation –use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) –decode the instruction (and read registers) –execute the instruction All instructions (except j ) use the ALU after reading the registers Fetch PC = PC+4 DecodeExec

Fetching Instructions Fetching instructions involves –reading the instruction from the Instruction Memory –updating the PC to hold the address of the next instruction –PC is updated every cycle, so it does not need an explicit write control signal –Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal Read Address Instruction Memory Add PC 4

Decoding Instructions Decoding instructions involves –sending the fetched instruction’s opcode and function field bits to the control unit –reading two values from the Register File Register File addresses are contained in the instruction Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit

Executing R Format Operations R format operations ( add,sub,slt,and,or ) –perform the (op and funct) operation on values in rs and rt –store the result back into the Register File (into location rd) –The Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File R-type: oprsrtrdfunctshamt 10 Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite