July 29, 2003Serguei Mokhov, 1 Makefile Brief Reference COMP 229, 346, 444, 5201 Revision 1.2 Date: July 18, 2004

July 29, 2003Serguei Mokhov, 2 Contents Intro Format Examples

July 29, 2003Serguei Mokhov, 3 Intro Makefiles in conjunction with the make utility ( man make ) provide a very convenient facility to build, install, and uninstall large (and small too) projects in the *nix systems. Makefiles are text files and similar in a way to the shell scripts, which are interpreted by the make utility.

July 29, 2003Serguei Mokhov, 4 Intro (2) A makefile may have some variables declared for convenience then followed by rules on how to build a given target program. The variable part usually declares variables like which compiler to use across all the targets: –which compiler options to use, –where to look for libraries and include files, etc. The rules specify what's needed to build a specific part and how to do it, using shell commands.

July 29, 2003Serguei Mokhov, 5 Intro (3) The make utility avoids re-bulding targets which are up-to-date, thus, saving typing and compiling time a lot. Makefiles largely similar to the Project and Workspace files you might be used to from Visual C++, JBuilder, Eclipse, etc.

July 29, 2003Serguei Mokhov, 6 Specifying Targets When making all the stuff in your program typing make is enough. In certain cases, the make utility assumes target “ all ”, or most often the first target in the list. If you want to build a specific target just supply it as a parameter to make: make mytarget

July 29, 2003Serguei Mokhov, 7 Filenames When you key in make, the make looks for the default filenames in the current directory. For GNU make these are: –GNUMakefile –makefile –Makefile If there more than one of the above in the current directory, the first one according to the above chosen. It is possible to name the makefile anyway you want, then for make to interpret it: make -f

July 29, 2003Serguei Mokhov, 8 Basic Makefile Format Basic Format Summary: # Comments VAR=value(s) # Actually, it is a macro target: list of prerequisites and dependencies command1 to achieve target using $(VAR) [ command2]

July 29, 2003Serguei Mokhov, 9 Basic Makefile Format (2) Comments –Just like for most shell scripts, they start with ‘ # ’ Variables (make calls them macros) –Are assigned the same way as in bash: var=value –Used as: $(var) –Variables can be scalar as well as lists (‘arrays’)

July 29, 2003Serguei Mokhov, 10 Rules Rule or several of then are needed to direct compilation and building, installation, and clean up actions that depend on certain prerequisites. Basic components of a Rule are –Ultimate target of a rule, the goal –List of dependencies needed to be satisfied before this rule can be executed, the prerequisites –List of actions, or command, that are executed once all prerequisites satisfied to arrive to the target goal.

July 29, 2003Serguei Mokhov, 11 Targets Target name can be almost anything: –just a name –a filename –a variable There can be several targets on the same line if they depend on the same things. A target is followed by –a colon “:” –and then by a list of dependencies, separated by spaced The default target make is looking for is either all or first one in the file. Another common target is clean –Developers supply it to clean up their source tree from temporary files, object modules, etc. –Typical invocation is: make clean You are required to supply another target, called run, so that it makes sure your application is compiled and run just by typing: make run.

July 29, 2003Serguei Mokhov, 12 Dependencies The list of dependencies can be: –Filenames –Other target names –Variables Separated by a space. May be empty; means “build always”. Before the target is built: –it’s checked whether it is up-to-date (in case of files) by comparing time stamp of the target of each dependency; if the target file does not exist, it’s automatically considered “old”. –If there are dependencies that are “newer” then the target, then the target is rebuild; else untouched. –If you want to “renew” the target without actually editing the dependencies, “touch” them with the touch command. –If the dependency is a name of another rule, make descends recursively (may be in parallel) to that rule.

July 29, 2003Serguei Mokhov, 13 Actions A list of actions represents the needed operations to be carried out to arrive to the rule’s target. –May be empty. Every action in a rule is usually a typical shell command you would normally type to do the same thing. Every command MUST be preceded with a tab! –This is how make identifies actions as opposed to variable assignments and targets. Do not indent actions with spaces!

July 29, 2003Serguei Mokhov, 14 Line-Oriented Makefile is a line-oriented file. That means by the end of line a new line starts, it is either a new action or target or whatever. If your list of dependencies or a command are too long and you would like for them to span across several lines for clarity and convenience, you may do so, but you will have to escape the end of line by “\” at the end of each such a line. Make sure not to use tabs for such lines.

July 29, 2003Serguei Mokhov, 15 More Advanced Constructs List/array variables/macros can be assignment via the “ := ” operator. It is possible to use control-flow constructs within the actions part of a rule, such as for, if-then-else, test, etc. The syntax is that of bash. Implicit targets for files of specific extensions. “Macros” and “directives” for conditional variable definitions as well as to include other makefiles. Others... Not part of this “study” yet...

July 29, 2003Serguei Mokhov, 16 Examples Off the website.