TE-MPE-EP, VF, 11-Oct-2012 Update on the DQLPU type A design and general progress. TE-MPE Technical Meeting

TE-MPE-EP, VF, 11-Oct-2012 DQLPU: old configuration SYKO DQQDL#A DQQDL#B DQAMC Fip connector UHDS#1-#4 + Trigger Vtaps Current Loop 230VAC Front view Rear view Fip connector

External and mechanical modifications to the enclosure TE-MPE-EP, VF, 11-Oct cm 2 Hinges

No cabling between back panel and motherboard TE-MPE,EP, VF, 11-Oct-2012 Burndy connectors for pcb Harting pins for pcb adapters Voltages Vtaps spacers

Internal hardware change after new implementation TE-MPE-EP, VF, 11-Oct-2012 Motherboard (viewed from inside) DQQDL A/B : local redudancy quench detectors. Harting Han E modules: Vtaps connector. Harting Han 32 B: Power supplies connector. DQCSU: Crate supervision unit: to monitor all voltages + test presence of the current in the loop + remote power cycling. Burndy 8 for signals from current transformers. SPARE: For futur upgrades. Burndy 12 for UDQHDS and trigger signal + another Burny 8/12 for spare. DQHSU: Quench heater supervision unit. To record fast current and voltage during a discharge of DQHDS. Burndy 12 (2x): Input and output current loop. DQAMC: Communication board to the supervision. 4TE front panel: Fip connector + reprogramming connector for DQAMC and DQCSU. = Futur emplacement for nanoFip board. FIP con./PROG. DQQDL#A DQQDL#B DQCSU SPAREDQHSU DQAMC V taps Voltage power supplies DQHSU Input signals UHDS+trigger and Spare I loop in/out

Status for boards and connectors: Motherboard: to be designed according to a few final decisions to be taken after some tests are performed. DQQDL: re-use all old DQQDL with new firmware. 200 new DQQDL in more exposed areas received and to be tested. DQCSU: prototype for all analog and digital stages done and tested. Quotes for components requested. DQHSU: second prototype with a relay installed on it to monitor the fuse inside the DQHDS. To be tested (Jens). Still minor modification to be done. An ultimate prototype will be needed. Most of components ordered. DQAMC: re-use of all old DQAMC with new firmware. Spares in the pipeline. Harting Han 32B: still waiting for information about adapting the length of pins and if Harting can produce a complete pcb adapter (set of 32 pins linked together). Harting Han E modules: individual assembling of 6 pins or one set of 6. Transmission of signals from current pulse transformers to the motherboard: tests to be performed to verify the quality of the transmission of signals before acceptance of a burndy connector. If unsuccessful, BNC connectors would be the alternative. TE-MPE-EP, VF, 11-Oct-2012

What can be re-used Burndy 12 M-M cable: For UHDS measurement and trigger. -Harting Han E module: Entire cable from Crawford box Connector from DQLPU: For Voltage taps. Syko (trivolt switching mode power supplies): re-used in DQLPU type B (Quad) for redundancy (4 x SYKO) DQQDL (2x), DQAMC TE-MPE-EP, VF, 11-Oct-2012

Firmware changes 1.Transmission of new signals for quench heater supervision and crate supervision. 2.Implementation of additionnal commands sequences for specialists: e.g. power cycling, device configuration. 3.Adaption to the new layout of the QPS fieldbus: macro-cycle length change from 200 ms  100 ms: higher transmission rate but much higher data volume. 4.Visibility board A and B, separate post-mortem buffers from board A / B and quench heater supervision. 5.Developmnent started as well as integration into QPS high level supervision. 6.Homework for the user: development of automatic analysis tools for quench heater supervision. TE-MPE-EP, VF, 11-Oct-2012

Conclusion Real advantages of this update and new supervision: Complete redundancy of linear power supplies. Quick diagnostic if loop interrupted. Current and voltage discharge  detection of a possible defect in a heater. Automatised discharge at low voltage after quench or spurious discharge of DQHDS  monitor heater before continuing. Much more data due to increase of sampling. Time acceptable thanks to the doubling of the wordfip network and a change in the firmwares (macro-cycle reduced from 200ms  100ms). Advantage of a completely new hardware design: a lot of time during tests saved basically due to the process of assembling the motherboard. No defect due to bad connections possible. TE-MPE-EP, VF, 11-Oct-2012

Thank you !