Outlier Detection in Capacitive Open Test Data Using Principal Component Analysis Xin He, Yashwant Malaiya, Anura P. Jayasumana Kenneth P. Parker and Stephen Hird

Outline Introduction Test Data Analysis & Results ---Capacitive Lead Frame Testing ---PCA Based Outlier Detection Test Data Analysis & Results ---Global Analysis ---Localized Analysis Summary and Future Work

Capacitive Lead Frame Testing good open Capacitance is formed between the tested pin and sense plate Open defect existing on tested pin affects the normal signal level Ref: Parker, Hird ITC 2007

Principal Component Analysis (PCA) The 1st Principal Component 1st Principal Component is the axis containing largest variance from the data projection 2nd Principal Component is an axis orthogonal to the 1st one, containing as much of the remaining projected variance The 2nd Principal Component Measurement2 Measurement1 Is good at analyzing multi-dimensional interrelated data.

PCA for PCB Outlier Detection Let M be (mxn) matrix of Capacitive Lead Frame Testing measurements - m is the number of boards - n is number of tested pins per board M Mc Centering:

PCA for PCB Testing Mc = USVT where Using Singular Value Decomposition, Mc = USVT where Umxn gives scaled version of PC scores Snxn diagonal matrix whose squared diagonal values are Eigen values arranged in ascending order. VTnxn contains Eigen vectors (PCs). V is the transformation matrix. Matrix Z = McV gives the z-score value of boards. Z-score value of a board is a linear combination of all the corresponding measurement values for that board.

Test Statistic for Outlier Detection zik : the value of the kth PC for the ith board E : a subset of PCs --- most significant PCs are used here Sort the boards with respect to the d1 Plot the cumulative distribution function (CDF) curve of d1 Outliers are clearly identifiable on the right side of the plot, and typically are separated from other devices by a clear margin

Test Data Data Name Board Runs Tested Pins Data_j27 15 147 Data_j24 83 145 Courtesy of Agilent Technologies

Global Analysis - (Data_j27) 3 1 Total 15 board runs First 5 PCs are used Clear outliers: 2, 3 and 1

Global Analysis - (Data_j24) 17 18,19,20,21,22 Total 83 board runs First 5 PCs are used Clear outliers: 17, 18, 19, 20, 21, 22 10

Pins in white color are VDD/grounded pins Localized Analysis Pin 1 Pin 120 Pin 121 Pin 240 Pins in white color are VDD/grounded pins

PCA Applied on Test Windows (Data_ j24) 1 2 3 4 5 6 7 8 9 10 …… Test Window 1 Test Window 10 12 12

Comparison of Global and Localized Methods Pass Fail (ii) (i) (i) Sharp peak signal may exist, other measurements matches well (ii) Slight variation exist in multiple pins measurement 13 13

Comparison of Global and Localized Methods (Example) 6 4

PCA Flow Chart Measurement matrix M (m boards n tested pins) Sort matrix according to pin location Center matrix in each group Derive Z scores for each group Divide to w test windows (w=1 for Global Analysis) Evaluate d1 values in each group Pass/Fail decision & outlier location Compare maximum d1 value in different groups Sort d1 Value

PCA vs. Standard Deviation (STDev) Average + N*STDev Average Average - N*STDev 16

PCA vs. STDev N Abnormal PCB Detected Board runs No. 6 5.5 1 17 5 4.5 5.5 1 17 5 4.5 2 14, 17 4 3,11,14,17,83 3.5 11 3,4,5,6,8,11,14,15,17,59,83 3 18 3,4,5,6,8,9,11,14,15,16,17,18,19,20,21,51,59,83 2.5 35 3,4,5,6,7,8,9,11,12,13,14,15,16,17,18,19,20,21,22 ,34,36,47,48,51,53,57,58,59,60,63,68,73,80,81,83 17

PCA vs. STDev PCA detected outliers: board run 17, 18, 19, 20, 21, 22 14 3 83 11 PCA detected outliers: board run 17, 18, 19, 20, 21, 22 18

Summary PCA can effectively identify outlier boards Localized analysis can increase test resolution and assist in the location of outliers The global and localized analysis can be combined to filter the outliers It can also be applied to other kinds of PCB test data beside Capacitive Lead frame test data

Future Work On-line testing techniques to enhance the detection efficiency Investigate data variation caused by measurement errors, mechanical and electrical tolerances Technique to compensate for the effects of mechanical variations, parameter variations, etc.