Conversion from one number base to another Equation simplification Conversion to/from SOP/POS Minimization using Karnaugh Maps Minterm and Maxterm Equations Determining Prime Implicants and Essential Prime Implicants Logical completeness Using MUXs and ROMs to implement logic Timing Analysis The internal structure of flip-flops Flip-flop timings Rising and falling edge triggered flip-flops Counters and state machines Generating next state equations from counter sequences. Implementation using RS, D, T and JK flip-flops Determining next states from schematics Moore vs. Mealy State Graphs Completeness and conflict issues Creating transition tables and next state equations from state graphs Verilog code One-hot encoding LC3 control UART Review for Final Exam

Conversion from one number base to another

Equation simplification (X + Y)(X + Z) = (X + YZ) X + XY = X X + X’Y = X + Y X + XY = X

Conversion to/from SOP/POS (X + YZ) = (X + Y)(X + Z)

Minimization using Karnaugh Maps AB CD AB + C’D + A’B’C + ABCD + AB’C AB + C’D + B’C

Minterm and Maxterm Equations F(ABCD) =  m (0,2,4,7,9,12,14,15) AB CD BC’D’ + BCD + ABC + A’B’D’ + AB’C’D

Determining Prime Implicants and Essential Prime Implicants AB CD x 11xx prime implicants 3 essential prime implicants

Logical completeness Inverter AND gate NAND AND gate Inverter OR gate

Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 for AB=00, Z=0 0

Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 for AB=01, Z=1 1

Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 for AB=11, Z=C’ C’

Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0

Implementing Logic Functions With Muxes An alternate method 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0 Z = A’B + BC’ A=0 B=0 A=0 B=1 A=1 B=0 A=1 B=1 Z = C’ = 0 Z = C’ = 1 Z = C’ = 0 Z = C’ = C’

Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

Timing Analysis A B AB E C D CD F E+F X

The internal structure of flip-flops R S Q Q’ GATE GS GR D Q’ Q GATE D CLK Q Q’ D-type Flip-Flop

The internal structure of flip-flops T-type Flip-Flop CLK Q Q’ T

The internal structure of flip-flops JK-type Flip-Flop CLK Q Q’ J K

Flip-flop timings Clock-to-Q D CLK Q Q’ t CLK ! Q = t NOT + t AND + 2 x t NOR

D CLK Q Q’ t setup = t NOT + t AND + 2 x t NOR Flip-flop timings Setup time

D CLK Q Q’ t hold = t NOT Flip-flop timings Hold time

Flip Flop Timing CLK D Q t setup t hold t CLK ! Q time

D CLK Q Q’ Falling Edge Triggered DFF Rising and falling edge triggered flip-flops

Rising Edge Triggered DFF D CLK Q Q’ Rising and falling edge triggered flip-flops

Generating next state equations from counter sequences. Desired count sequence = … If current state = 00, next state = ????? Implemented count sequence = … N2 = Q2 Q1’ + Q1’ Q0 N1 = Q2 N0 = Q2’ Q0’ + Q1 Q0’

Implementation using RS, D, T and JK flip-flops

Determining next states from schematics Q0 Q2 CLK Q1 CLK Q2 D Q Q2 Q1’ Q0 Q2’ Q0’ Q1 Q0’ Q2 Q1 Q Initial state

Moore vs. Mealy

For general purpose FSMs, the encoding of the states is usually not significant For example, in the following state graph, the Encodings of the state are irrelevant … Event 1 Event 2 Event 1 Event 2Event 3

Completeness Issues In order for a state graph to be complete: It must completely specify the FSM Paths leaving a state must specify all POSSIBLE cases To check for completeness, OR together all of the exiting paths. If the result is “1” then the design is complete.

In order for a state graph to be conflict free: It must completely specify the FSM For a given set of input conditions, the transition from a state must be unique To check for conflicts, AND together all pairs of the exiting paths. If the result is “0” for all pairs, the design has no conflicting transitions. Conflict Issues

Creating transition tables and next state equations from state graphs

The resulting next state and output equations are: N1 = Q0 + Q1 TDONE’ N0 = TOKEN Q1’ Q0’ CLRT = Q0 SPRAY = Q1

Dataflow Operators

IR ALU PC AB

LC-3 Instructions ADD 0001 DR SR1 00 SR2 0 ADD 0001DRSR1 imm5 1 AND 0101 DR SR1 00 SR2 0 AND 0101DRSR1 imm5 1 BR 0000n z p PCoffset9 JSR JMP BaseR LD 0010PCoffset9 DR LDI 1010PCoffset9 DR LDR 0110offset6 DR BaseR LEA 1110PCoffset9 DR NOT 1001 DR SR RET 1101 RTI STR 0111offset6 SR BaseR TRAP 1111trapvect80000 ST STI 0011 PCoffset9 SR 1011 PCoffset9SR PCoffset reserved JSRR BaseR