 Seattle Pacific University EE Logic System DesignSOP-POS-1 The Connection: Truth Tables to Functions abcF abcF Function F is true if any of these and-terms are true! Condition that a is 0, b is 0, c is 1. OR Sum-of-Products form

 Seattle Pacific University EE Logic System DesignSOP-POS-2 Minterm Shorthand = m 0 = m 1 = m 2 = m 3 = m 4 = m 5 = m 6 = m 7 Note: Binary ordering A minterm has one literal for each input variable, either in its normal or complemented form. A canonical sum-of-products form of an expression consists only of minterms OR’d together abcF abcF

 Seattle Pacific University EE Logic System DesignSOP-POS-3 Minterms of Different Sizes Two variables: abminterm 00a’b’ = m 0 01a’b = m 1 10a b’ = m 2 11a b = m 3 Three variables: abcminterm 000a’b’c’ = m 0 001a’b’c = m 1 010a’b c’ = m 2 011a’b c = m 3 100a b’c’ = m 4 101a b’c = m 5 110a b c’ = m 6 111a b c = m 7 Four variables: abcdminterm 0000a’b’c’d’ = m a’b’c’d= m a’b’c d’ = m a’b’c d= m a’b c’d’= m a’b c’d= m a’b c d’= m a’b c d= m a b’c’d’ = m a b’c’d= m a b’c d’ = m a b’c d= m a b c’d’ = m a b c’d= m a b c d’ = m a b c d= m 15

 Seattle Pacific University EE Logic System DesignSOP-POS-4 Sum-of-Products Minimization F in canonical sum-of-products form (minterm form): Use algebraic manipulation to make a simpler sum-of-products form Use commutativity to reorder to group similar terms Use distributivity to factor out common terms Use x’+x = 1 identity Duplicate term - OK We will find a better method (K-maps) later…

 Seattle Pacific University EE Logic System DesignSOP-POS-5 Product-of-Sums from a Truth Table A B C F F Use DeMorgan’s Law to re-express as product-of sums Find an expression for F’ (the complement) Complement both sides…

 Seattle Pacific University EE Logic System DesignSOP-POS-6 Maxterms A B C F F To find a Product-of-Sums form for a truth table Make one maxterm for each row in which the function is zero For each maxterm, each variable appears once In its complemented form if it is one in the row In its regular form if it is zero in the row Maxterms

 Seattle Pacific University EE Logic System DesignSOP-POS-7 Maxterm Shorthand Product of Sums F in canonical maxterm form: A B C Maxterms A + B + C = M 7 A + B + C = M 6 A + B + C = M 5 A + B + C = M 4 A + B + C = M 3 A + B + C = M 2 A + B + C = M 1 A + B + C = M

 Seattle Pacific University EE Logic System DesignSOP-POS-8 Boolean operations and gates Theorem: Any operation than can be represented by a truth table can be represented in Boolean algebra All truth tables can be made out of only and, or, and not functions

 Seattle Pacific University EE Logic System DesignSOP-POS-9 NAND/NOR expressions Any expression can be made of and ANDs, ORs and NOTs Thus, we can make any expression out of NANDs, NORs, and NOTs So, we can make any expression out of just NANDs and NORs X X note: NANDs and NORs are easy to build with switches We can make ANDs and ORs from NANDs and NORs and NOTs We can make NOTs out of a single NAND gate

 Seattle Pacific University EE Logic System DesignSOP-POS-10 NAND-only circuits Using DeMorgan’s Law NORs can be made with NANDs! We can make any Boolean expression out of only NAND Gates NANDs can be made out of NORs! We can make any Boolean expression out of only NOR Gates

 Seattle Pacific University EE Logic System DesignSOP-POS-11 Sum-of-Products Circuits with NANDs Introduce Double Inverters Sum-of-Products works well with NANDs DeMorgan’s Law

 Seattle Pacific University EE Logic System DesignSOP-POS-12 Product-of-Sums Circuits with NORs Introduce Double Inverters Product-of-Sums works well with NORs DeMorgan’s Law

 Seattle Pacific University EE Logic System DesignSOP-POS-13 Converting General Circuits to NANDs A B D C B A C D B D Introduce Double Inverters to make NANDs: Add inverters as needed to maintain correct polarity Represent inverters with NANDs        

 Seattle Pacific University EE Logic System DesignSOP-POS-14 Seven-Segment Example A seven-segment display is used to display numbers a b c d e f g a b c d e f b ca b d e ga b c d gb c f ga c d f ga c d e f ga b ca b c d e f ga b c d f g

 Seattle Pacific University EE Logic System DesignSOP-POS-15 Seven Segment Truth Table Inputs: Four binary inputs, interpreted as a four-bit binary number Outputs: Seven outputs, for each of the seven segments numberABCDabcdefg xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx Invalid inputs, assume zero segment a = A’B’C’D’ + A’B’CD’ + A’B’CD + A’BC’D + A’BCD’ + A’BCD + AB’C’D’ + AB’C’D (canonical SOP) segment a = A’C + A’BD + AB’C’ + B’C’D’ (minimal SOP) segment a = (A+B+C+D’) (A+B’+C+D) (canonical and minimal POS)

 Seattle Pacific University EE Logic System DesignSOP-POS-16 Circuits for Segment a segment a = A’C + A’BD + AB’C’ + B’C’D’ (minimal SOP) segment a = (A+B+C+D’) (A+B’+C+D) (canonical and minimal POS) ABCD a A B CD A B C D a