AIDA: LEC-HEC connection Davide Braga Steve Thomas ASIC Design Group 16September 2010

2 New link between low and high channels: In this technology forward-biased diodes suffer of parasitic bipolar structure to the substrate. -increased the size of clamp transistor to reduce resistance (~100s Ohm) -diodes have been replaced with diode- connected transistors: they are effective but slower (for the charge to flow they need to wait for the creation of the channel) and susceptible to threshold variation

3 Parametrized input current: d e-e- h+h+ 3d Q/6d Q/2d d=1 d=2 d=3 Only one parameter d to model the input charge: for a given area (charge Q) d is swept to simulate increased collection time from the detector. NB: this does not account for plasma effect in the detector so expect pessimistic simulations for high energy implants! NB2: input capacitance C in =10pF

4 High ref, Qin=900pC (~18GeV) (1): Vin (d=100ns) -with input diode-connected transistors -without Vin (d=200ns) no significant difference between the two, the diode- connected transistors don’t conduce Vin (d=300ns) Input Current: charge (area) and shape constant but different collection times from detector HEC preamp out (d=100ns) -with input diode-connected transistors -without (charge loss)

5 High ref, Qin=900pC (~18GeV) (2): Input current (d=100ns-200ns-300ns) Vin Charge flowing through diode connected transistors HEC preamp output Charge flowing through clamp transistor

6 High ref, Qin=900pC (~18GeV) (3): Charge flowing through clamp transistor (d=100ns-200ns-300ns) HEC preamp output for different d Sampled value once the output has settled For the fastest collection time (d=100ns) we lose ~5% of the input charge Charge flowing through diode-connected transistors

7 High ref, Qin=900pC (~18GeV) (4): Current in the diode- connected transistor equivalent resistance (detail)

8 High ref, Qin=500pC (~10GeV) (1): Input current (d=50ns-100ns-150ns) Vin HEC preamp output Comparator switching in OK if d~>100ns

9 High ref, Qin=500pC (~10GeV) (2): Vin (d=50ns-100ns-150ns) HEC preamp output (detail): no charge loss for d~>100ns Charge transferred to the HEC (loss for d=50ns) for d=50ns we lose 5.7% of input charge. NB: no ballistic deficit considered HEC preamp output Charge lost in a forward- biased pmos in the LEC

10 High ref, Qin=100pC (~2GeV): Input current (d=20ns-40ns-60ns) Vin Within power supplies

11 High ref, Qin=50pC (~1GeV): Input current (d=10ns-30ns-50ns) Vin Within power supplies

12 Low ref, Qin=900pC (~18GeV) (1): Input current (d=100ns-200ns-300ns) Vin Input voltage shouldn’t reverse-bias the substrate even in worst case (d=100ns) HEC preamp output Comparator switching in

13 Low ref, Qin=900pC (~18GeV) (2): Current in the diode- connected transistor equivalent resistance (detail)

14 Low ref, Qin=500pC (~10GeV): Input current (d=50ns-100ns-150ns) Vin Input voltage shouldn’t reverse-bias the substrate if d~>100ns HEC preamp output Comparator switching in

15 Low ref, Qin=100pC (~2GeV): Input current (d=20ns-40ns-60ns) Vin Input voltage shouldn’t reverse-bias the substrate if d~>40ns HEC preamp output Comparator switching in

16 Low ref, Qin=50pC (~1GeV): Input current (d=10ns-30ns-50ns) Vin Input voltage shouldn’t reverse-bias the substrate if d~>30ns HEC preamp output Comparator switching in