Development of Advanced MAPS for Scientific Applications Jamie Crooks CMOS Sensor Design Group Rutherford Appleton Laboratory UK FEE Workshop 2009

Overview Aim to give a summary of MAPS activity at RAL Technology 4T pinned photodiode Quadruple-well CMOS High resistivity substrates Stitching Example pixels 4T pixel 160T pixel Summary FEE Workshop 2009

CMOS Sensor Design Group at RAL Work on CMOS image sensors at RAL began in 1998 The CMOS Sensor Design group was established in 2006 Currently has eight members, led by Renato Turchetta The group designs CMOS image sensors for many applications including… particle physics space science medical imaging high-end commercial projects FEE Workshop 2009

MAPS requirements for Science Low noise High sensitivity Radiation tolerance Large pixels Often the <2um pixels from industry are not necessary Large sensing areas Uninterrupted or minimum “dead space” Sparse readout Region-of-Interest readout Advanced pixel functionality Pedestal correction Analog preamplifiers Thresholding Event timing ADC Memories Global shutter Technology developments… FEE Workshop 2009

4T Pinned Photodiode Technology… Sensitivity (conversion gain) is set by the capacitance of the floating diffusion, not the diode Can be optimised for target application Architecture permits correlated double sampling Low noise performance Pinning layer creates buried diode Transfer of charge to the floating diffusion aided by electric field The diode is fully depleted following a transfer (ie “reset”) Integrate signal Reset Read Transfer P+ layer pins the surface of the diode to the substrate TX gate applies the “pinning voltage” (doping dependant) to the n layer Diode becomes fully depleted allowing noiseless transfer This is not PIN diode! FEE Workshop 2009

CMOS Imaging Technology… MAPS pixels generally exclude PMOS transistors Their N-well reduces charge collection efficiency Applies to light / particles Regular imaging applications generally have no need for PMOS transistors in the pixel Scientific applications sometimes do FEE Workshop 2009

Deep P-Well Technology… We developed a “Deep P-Well” in collaboration with a leading CMOS image sensor foundry High energy implant creates a deep p-well Selectively drawn “under” n-wells in pixels Change in doping creates a potential barrier Diffusing charge is reflected back and not collected by the n-well FEE Workshop 2009

Deep P-Well Implementation Device simulations TCAD uses gds of pixels Charge diffusion is modelled Layout Drawn layer with design rules Manufacturing MPW run is divided some wafers receive DPW, others do not Enables comparison of performance FEE Workshop 2009

Substrate Resistivity Technology… Substrate Resistivity Reference schematic Pixel with deep p-well Depletion region illustrated Standard resistivity wafer Diffusing charge that reaches the depletion region is collected by electric field FEE Workshop 2009

Substrate Resistivity Technology… Substrate Resistivity Increased resistivity silicon enlarges the depletion region Diffusing charge that reaches the depletion region is collected by electric field Improved charge collection efficiency by larger catchment area FEE Workshop 2009

Substrate Resistivity Technology… Substrate Resistivity High resistivity (intrinsic) silicon enlarges the depletion region to fully occupy the pixel Majority of deposited charge now falls in a depletion region and is collected by electric field Improved charge collection efficiency Faster charge collection (drift vs diffusion) FEE Workshop 2009

INMAPS Process Technology… 0.18 micron commercial CMOS Imaging Process 4T pinned photodiodes Choice of epitaxial layer thickness Deep p-well High resistivity substrates Stitching Multi-project runs for prototyping Option to vary starting material & implants per wafer 9 multi-project submissions in last 2 years… FEE Workshop 2009

Examples… Current Projects FORTIS TPAC FEE Workshop 2009

Current Projects FORTIS TPAC Examples… Optical/Particle applications 4T Test Image Sensor FORTIS TPAC Optical/Particle applications Explores 13 variants of a 4T pinned photodiode Diode size Pixel pitch Pixel geometry FEE Workshop 2009

4T Test Image Sensor Development project Design parameters Geometry Manufacturing parameters DPW Substrate material Optimised implants FORTIS Pixel Pitch Diode size Source follower Active area Epitaxial Layer Deep P-Well Hi-Res wafer All pixels: FEE Workshop 2009

4T Pixel Characterisation Photon Transfer Curve image-sensor standard test Conversion gain = 61μV/e- Noise (equivalent) = 5.9e- 55Fe Photons (preliminary) Conversion gain = 56 μ V/e- Noise (from dark fwhm) = 7.7e- FEE Workshop 2009

4T Pixel Test Programme 100 different pixels to test! Pixel characterisation PTC, Image Lag, 55Fe Pixel design Pairs of pixel give direct comparison of key feature Processing Optimal implants Confirm DPW and 4T are compatible Functional design on high-resistivity substrate Charge collection efficiency Radiation tolerance (in progress) Fully characterised sensors 50KV x-ray tube Incremental doses from 105 MRad Repeat characterisation after irradiation Beam test CERN beam test with EUDET pixel telescope in August Evaluation of 4T architecture for particle physics applications 100 different pixels to test! FEE Workshop 2009

Tera-Pixel Active Calorimeter Examples… Current Projects Tera-Pixel Active Calorimeter FORTIS TPAC Optical/Particle applications Explores 13 variants of a 4T pinned photodiode Diode size Pixel pitch Pixel geometry Particle detection Implements in-pixel circuits preAmplifier + shaper comparator + logic SRAM configuration memories FEE Workshop 2009

Tera-Pixel Active Calorimeter SiW Digital ECAL for ILC 30 layers silicon & tungsten Demonstrate Monolithic Active Pixel Sensor (MAPS) as a viable solution for the silicon Sensor Specification Sensitive to MIP signal Small pixels determine “hit” status (binary readout) Store timestamp & location of “hits” Target noise rate 10-6 Design to hold data for 8k bunch crossings before readout Minimum “dead space” FEE Workshop 2009

TPAC Pixel Gain 136uV/e Noise 23e- Power 8.9uW 150ns “hit” pulse wired to row logic Shaped pulses return to baseline 50um pixel 4 diodes 160 transistors 27 unit capacitors 1 resistor (4Mohm) Configuration SRAM Per Pixel Mask Comparator trim (6 bits) FEE Workshop 2009

TPAC Pixel PO Gain 136uV/e Noise 23e- Power 8.9uW 150ns “hit” pulse wired to row logic Shaped pulses return to baseline 50um pixel 4 diodes 160 transistors 27 unit capacitors 1 resistor (4Mohm) Configuration SRAM Per Pixel Mask Comparator trim (6 bits) M1 NW DPW FEE Workshop 2009

TPAC Architecture 8.2 million transistors 28224 pixels; 50 microns; 4 variants Sensitive area 79.4mm2 of which 11.1% “dead” (logic) Four columns of logic + SRAM Logic columns serve 42 pixels Record hit locations & timestamps Local SRAM Data readout Slow (<5Mhz) Current sense amplifiers Column multiplex 30 bit parallel data output FEE Workshop 2009

TPAC Test Programme TPAC1.0 Test pixels TPAC1.0 Array pixels 1.0 Charge collection profile (laser) Compare with device simulation TPAC1.0 Array pixels Two variants of the pre-shaper pixel Pedestal variation  trim adjustment Gain uniformity TPAC1.1 Test pixels Gain & noise calibration (55Fe) TPAC1.1 Array pixels Capacitive coupling problem 1.0 4 pixel variants in array Two “sampler” test pixels Different epi thicknesses With/without DPW 1 pixel variant in array Two “shaper” test pixels Upgraded 4 6 trim bits Improved matching of R With/without DPW Standard & Hi-Res Substrates 1.1 Shielding added in pixel 1.2 FEE Workshop 2009

Charge collection efficiency 2x2μm focussed IR laser spot 1064nm laser The laser is raster-scanned over an 200x200 area The test pixel is surrounded by dummy neighbours Signal magnitude (mV) is plotted in the z (colour) axis for each position of the laser spot Averaged (50 samples) The overlaid pixel structure shows n-wells (solid line) and deep p-well (dotted line) FEE Workshop 2009

Measured vs Simulation Results Amplitude results With/without deep pwell Qualitative comparison Simulations “GDS” Measurements “Real” Pixel profiles F B FEE Workshop 2009

Charge collection (diffusion) time Timing measurement (30mV threshold) 17μm M Measured timing includes a fixed laser-fire delay TCAD Simulation (Q=90%) C B

Gain Calibration with 55Fe 55Fe photons will deposit 1620e- at random locations in the pixel volume The deposited charge will diffuse and be collected at several diodes A tiny fraction of these deposits will be within the depletion region of a single diode The full 1620e- will be collected This gives an absolute calibration of gain The histogram of recorded signals will show a peak for 1620e- Secondary peak at 1778e- FEE Workshop 2009

Histogram of 55Fe Events Low “threshold” on oscilloscope Investigates full distribution of hits High “threshold” on oscilloscope Investigates 55Fe peak With deep p-well Without deep p-well Kα peak fit Kβ peak fit Primary 55Fe peak gives calibrated gain of 128µV/e- Width of 55Fe peak gives noise of 27e- FEE Workshop 2009

Histogram of 55Fe Events Why the peak at ~30% signal? Basic diffusion model Deposit 55Fe at different heights Shows ~30% as a probable value Deep p-well prevents many deposits in pixel centre being collected They diffuse and tend to read as ~30% With deep p-well Without deep p-well ? Without DPW With DPW FEE Workshop 2009

TPAC Pixel Arrays Per-pixel noise Pixel gain uniformity Meas. by threshold scan Generate trim settings & load Pixel gain uniformity Laser stimulus Hit each pixel in turn Threshold scan 55Fe photons Use peak 12% 13% FEE Workshop 2009

TPAC Test Programme TPAC1.0 Test pixels TPAC1.0 Array pixels Charge collection profile (laser) Compare with device simulation TPAC1.0 Array pixels Two variants of the pre-shaper pixel Pedestal variation  trim adjustment Gain uniformity TPAC1.1 Test pixels Gain & noise calibration (55Fe) TPAC1.2 Test pixels Charge collection characteristics on high resistivity substrate TPAC1.2 Array pixels Pixel uniformity Noise performance Crosstalk/pickup Cosmics Beam test 4 layer stack FEE Workshop 2009

Stitching 61mm sensor 56mm sensor Allows a seamless pixel array up to 130x130mm on a 200mm wafer Same mask set can make different size sensors 61mm sensor 56mm sensor 22mm variant 11mm variant FEE Workshop 2009

MAPS Activity at RAL Our recent technology developments have achieved 4T pinned photodiode sensor <6e- noise Sensors with deep P-Well shown to preserve charge collection with full CMOS in a pixel Two MAPS designs manufactured on Hi-Resistivity Two stitched MAPS designs FEE Workshop 2009

Acknowledgements/Collaborators SPiDeR FEE Workshop 2009

Spare slides Stitching “animations” FEE Workshop 2009

Stitching 1 A B D C Optical reticle divided into 4 main areas for each chip Sensor is constructed by repeating the blocks N times to create larger device

Stitching 2 D B B B D A B D C C A A A C C A A A C C A A A C D B B B D Top sections contain pixel reset control circuits C A A A C C A A A C Left Edge contains row addressing and reset control circuits Bottom sections contain column addressing and analogue readout circuits 2 Outputs per section D B B B D

Stitching 3