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Department of Electronics Engineering Sahand University of Technology NMOS inverter with an n-channel enhancement-mode mosfet with the gate connected to the drain Farshad Gozalpoor Professor : Dr Najafi Aghdam winter 93 2

 We will analyze the dc voltage transfer characteristics of this inverter in this figure.  We will also define and develop the noise margin of this digital circuit in terms of the inverter voltage transfer curve.  We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels.  A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. Abstract 3

The drain current is zero. A nonzero drain current is induced in the device. We can see that the following condition is satisfied : A transistor with this connection always operates in the saturation region when not in cutoff. Diode connected transistor 4

 VIH = minimum HIGH input voltage  VIL = maximum LOW input voltage  VOH= minimum HIGH output voltage  VOL = maximum LOW output voltage Some definitions 5

HINT: In the following analysis, we neglect the body effect and we assume all threshold voltages are constant. These assumptions do not seriously affect the basic analysis or the inverter characteristics. The driver is cut off and the drain currents are zero. Assumptin : VTC computations M1 : Off M2 : Sat 6

M1: Sat M2: Sat 7

Computing Vin1 and Vo1 : 8

c) M1 : Triode M2 : Sat 9

:Assumption Vin=1.5 K1=20 K2=10 Vth=0.41v VO+ = VO - =

Computing VIH : 11

Analysis of the transient behavior of the gate Drain diffusion capacitances of the NMOS transistors, the capacitance of the connecting wires, and the input capacitance of the fan-out gates  A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor. 12

Switching Threshold We solve the case where the supply voltage is high so that the devices can be assumed to be velocity-saturated Where 13

For large values of VDD  It is considered to be desirable for VM to be located around the middle of the available voltage swing.  To move VM upwards, a larger value of r is required.  Increasing the strength of the NMOS, on the other hand, moves the switching threshold closer to GND. 14

Design Technique — Maximizing the noise margins  To balance the driving strengths of the transistors and maximize the noise margins and obtain symmetrical characteristics use this equation: Example: Switching threshold  VM is sensitive to variations in the device ratio 15

 We have sweeped the W of load transistor to see the effect of change in transistors size ratio on the VM 16

 This means that small variations of the ratio do not disturb the transfer characteristic that much. 17

The usage of shifting the transient region of the VTC by changing VM 18

Another example for VTC 19

Scaling the Supply Voltage  Continuing technology scaling forces the supply voltages to reduce at rates similar to the device dimensions.  At the same time, device threshold voltages are virtually kept constant. 20

 At a voltage of 0.2 V the width of the transition region measures only 10% of the supply voltage while it widens to 25% for 2.5 V  So, given this improvement in dc characteristics  why do we not choose to operate all our digital circuits at these low supply voltages?  reducing the supply voltage has a positive impact on the energy dissipation, but is detrimental to the performance on the gate.  The dc-characteristic becomes increasingly sensitive to variations in the device  parameters such as the transistor threshold, once supply voltages and intrinsic voltages become comparable. 21

D ELAY DEFINITIONS 22

First-Order Analysis Integrate the capacitor (dis)charge current:  i the (dis)charging current  v the voltage over the capacitor  v 1 and v 2 the initial and final voltage  Equivalent resistance when (dis)charging a capacitor: 23

 Equivalent resistance, averages the resistance of the device over the interval: 24

Example Assume that a driver with a source resistance of 10 kW is used to drive a 10 cm long, 1 mm wide Al1 wire with total lumped capacitance for this wire equals 11 pF The operation of this simple RC network is described by the following ordinary differential Equation: 25

When applying a step input, the transient response of this circuit is Where:  The time to reach the 50% point: t = ln(2)t = 0.69t  To get to the 90% point: t = ln(9)t = 2.2t  the propagation delay of such a network for a voltage step at the input is proportional to the time-constant of the network. 26

 the propagation delay of such a network for a voltage step at the input is proportional to the time-constant of the network: Example:  The overall propagation delay of the inverter: Propagation Delay of a 0.25  m Inverter 27

supply voltage equals to 2.5 V The (W/L) ratios of the transistors to be 1.5 for the NMOS1, and 4.5 for the NMOS2. 28

 make the parameters governing the delay explicit Propagation delay of inverter as a function of supply voltage 29

The propagation delay of a gate can be minimized in the following ways:  Reduce CL: three major factors contribute to the load capacitance: the internal diffusion capacitance of the gate itself, the interconnect capacitance, and the fanout.  Increase the W/L ratio of the transistors. This is the most powerful and effective performance optimization tool in the hands of the designer.  Increase V DD 30

 If symmetry and reduced noise margins are not of prime concern, it is possible to speed up the inverter by reducing the width of the PMOS device  The load capacitance of the first gate: 31

 By setting:  Sizing Inverters for Performance  Cint is associated with the diffusion capacitances of the NMOS and PMOS transistors as well as the gate-drain overlap (Miller) capacitance  Cext is the extrinsic load capacitance 32

 tp0 = 0.69 ReqCint represents the delay of the inverter only loaded by its own intrinsic capacitance (Cext = 0), and is called the intrinsic or unloaded delay 33

 The intrinsic delay of the inverter tp0 is independent of the sizing of the gate, and determined by technology and inverter layout.  Making S infinitely large yields the maximum performance gain, eliminating the impact of external load, and reducing the delay to the intrinsic one. Sizing A Chain of Inverters:  Determining the optimum sizing of a gate when embedded in a real environment.   is a proportionality factor, which is only a function of technology  Delay if the inverter is function of the ratio between its external load capacitance and input capacitance. This ratio is called the effective fanout f. 34

 The goal is to minimize the delay through the inverter chain  the optimum size of each inverter is the geometric mean of its neighbors sizes 35

 With Cg,1 and CL given:  Choosing the Right Number of Stages in an Inverter Chain  The optimum value can be found by differentiating the minimum delay expression by the number of stages, and setting the result to 0. For  = 0: Optimal number of stages equals N = Ln(F) Effective fan out of each stage is set to f = = e 36

 Optimum effective fanout f as a function of the self-loading factor  in an inverter chain  Normalized propagation delay (tp/(tpopt) as a function of the effective fanout f for  37

The rise/fall time of the input signal  propagation delay of a minimum-size inverter as a function of the input signal slope  Example: Delay of Inverter embedded in Network  an expression for the delay of the stage-2 inverter 38

 Power, Energy, and Energy-Delay  The power dissipation of an inverter is dominated by dynamic dissipation resulting from charging and discharging capacitances.  Dynamic Power Consumption  Dynamic Dissipation due to Charging and Discharging Capacitances 39

 This means that only half of the energy supplied by the power source is stored on CL  Example: Capacitive power dissipation of inverter  the value of the load capacitance was determined to equal 6 fF  For a supply voltage of 2.5 V 40

 switching activity f : maximum possible event rate of the inputs P0  1 : probability that a clock event results in a 0  1 event at the output of the gate. CEFF = P0  1CL is called the effective capacitance and represents the average capacitance switched every clock cycle Example: Switching activity Clock and signal waveforms  Power consuming transitions occur 2 out of 8 times, which is equivalent to a transition probability of 0.25 (or 25%). 41

 Example: Transistor Sizing for Energy Minimization inverter driving an external load capacitance Cext, while being driven by a minimum sized gate.  Degrees of freedom are size factor f of the inverter and supply voltage Vdd of the circuit.  f = 1 and Vdd = Vref. 42

 Sizing of an inverter for energy-minimization Required supply voltage as a function of the sizing factor f for different values of the overall effective fanout F Energy of scaled circuit (normalized with respect to the reference case) as a function of f. Vref = 2.5V, VTE = 0.5V. 43

 Static Consumption  Example: Impact of threshold reduction on performance and static power dissipation  0.25  m CMOS technology  slope factor S for this device equals 90 mV/decade  The off-current of the transistor for a VT of approximately 0.5V equals 10-11A  Reducing the threshold with 200 mV to 0.3 V multiplies the off-current of the transistors with a factor of 170! Decreasing the threshold increases the subthreshold current at V GS = 0. 44

 Putting It All Together: 45

 Some of remaining simulations Input Charatristics Input Output 46

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Input Charatristics Input Output 49

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Ring Oscillator 52

Transient simulation 53

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Thanks for your attention 56