1 Microprocessor-based systems Course 6 Memory design

2 Memory circuits  Memory cell: A digital circuit that memorize one bit (e.g.: flip-flop)  Memory location (memory word) Set of elementary memory cells accessed (read or written) simultaneously The basic addressing element (1, 4, 8,16, 32 bits) Every location has an address  Memory circuit = Set of memory locations  Memory capacity – total number of locations (addresses) bk...b1b n-1 Linear structure addresses locations bk...b1b0 location Lines columns 012..c l-1 Matrix structure

3 Characteristics of a memory circuit  Geometry of internal organization: The length of the memory word, organization and addressing.  Memory capacity, Expressed in number of memory locations or in bytes For example:32 kbytes, 64 kB, 256MB, 1GB.  Volatility: loss of data ROM memory (Read Only Memories) – keeps/stores the data even when the power supply is switched off  ROM, PROM, EPROM, EEPROM, Flash RAM memory (Random Access Memories): it looses its content if the power supply is switched off  Static RAM (SRAM) High speed, low capacity  Dynamic RAM (DRAM): it looses its memory in time Medium speed, very high capacity

4 Characteristics of a memory circuit  Memory technologies: bipolar (TTL, TTL Shottky, ECL) – fast but low integration ratio, high power consumption MOS, CMOS – high integration ratio, high capacity, average speed, small power consumption  Time features: Access time: the time needed to read or write a memory location; expressed in nanoseconds [ns]. The duration of a read or write cycle The memory’s speed determined by its access time or transfer cycle  Power consumption, expressed in w/bit. Bipolar memories have higher power consumption; it depends on the capacity MOS memories have very low power consumption; it depends on the access frequency

5 Non-volatile memories: ROM, PROM EPROM, EEPROM, Flash ADDR DEC Data Amplifiers for read and programming A0 A1 An Control logic CS PROG OE DkDk-1 D1 D0 ADDR DATA Valid Address Valid Data t ACC T CYCLE t OE t CS t OH CS OE a. b.  The internal structure of a ROM memory

6 Non-volatile memories: ROM, PROM EPROM, EEPROM, Flash  ROM – Cannot be written, only read operations are allowed Written by the producer (through masks)  PROM – Programmable ROM - One write (programming) operation is allowed for the used  EPROM (UV) – Erasable PROM – a limited number of erase and re-write operations are allowed (aprox. 100 cycles)  EEPROM – Electrically EPROM – electrical erase and re-write (aprox cycles)  Flash – type of EEPROM with a block organization and higher capacity WL DL T ROM WL DL T PROM Vcc  F WL DL T1 EPROM PL T2

7 Static RAM memories ADDR DEC Input/output circuit A0 A1 An-1 Control logic CS Dk-1 Dk-2 D1 D0 Input amplifier Output amplifier kk Memory matrix ADDR DATA Valid address Valid Data t ACC T CITIRE CS R/W “1” t CD Internal structure b1. ADDR DATA Valid address Valid Data T SCRIERE t DM CS R/W Time diagrams for read and write operations WR

8 Structure of RAM memory ID k-1 CS D C QQ D C QQ D C QQ D C QQ D C QQ D C QQ D C QQ D C QQ D C QQ ID 1 ID 0 OD k-1 OD 1 OD 0 R/W ADDR DEC A0A0 A1A1 A n-1

9 Dynamic RAM memory  The elementary memory cell is a condenser It is charged (logical 1) or not (logical 0) at write operation; The charge is lost in time (in aprox. 2 ms)  High capacity  Requires refresh operations Raw addr. dec MUX / DMUX 2 n/2 -1:1 / 1: 2 n/2 -1 A0 A1 An/2-1 ID Raw address reg Column address reg n/ n/ n/2 RAS CAS OD WE WL/R DL T3 WL/W C T1 T2 DRAM Memory cell

10 Read, write and refresh cycles for DRAM memory Column addr. CAS ADDR DATA Raw addr Valid data T READ RAS WE Read cycle Column addr. CAS ADDR DATA Raw addr Valod data T WRITE RAS WE Write cycle CAS ADDR Raw addr T refresh RAS WE Refresh cycle

11 Design of a static RAM memory module  The structure of a memory module Addresses Data Selection Address Amp. Data Amp. Metrix of memory circuites Control circuit Dec Module selection Commands

12 Design parameters Memory capacity (KB, MB) Internal organization (ex: 8, 16, 32 bits) The bus: Address lines, data lines and commands Time restrictions Start address (the module’s place in the addressing space of the processor) Type of available memory circuits Other functional requirements

13 Design steps 1. Building of a memory sub-module with the required data width 2. Build the memory matrix with the required capacity, using the previously built sub-modules 3. Design the decoder module 4. Design of address amplifiers 5. Design of data amplifiers 6. Design of the control circuit (if needed)

14 Design example  Capacity: 1Mbytes  Organization: 16 bits with access on 8 bits too  The bus: ISA (24 address lines, 16 data lines, MRDC, MWTC)  Start address: C0000H  Available circuits: 64Kbytes

15 Building a sub-module with the required data width 64K *8 A1A2A1A2 A 16 WR\ CSH i \ CSL i \ D0D0 D1D1 D8D8 D7D7 D 15 D9D9 Submodule 64K*16= 128K*8

16 Building the memory matrix with the required capacity A 1 -A 16 64K *16 … D 0 -D 15 WR\ CSL 0 \ CSH 0 \ CSH 1 \ CSH 7 \ CSL 1 \ CSL 7 \ 512K*16=1M*8

17 Design of the decoder unit CS 0 \ CS 1 \ CS 7 \ A 17 -A 23 MRDC\, MWTC\ DEC SelMod\ 74LS 138 A 17 A 18 A 19 A 23 A 22 A 21 A 20 MRDC\ MWTC\ BHE\ A 0 CSL 0 \ CSH 0 \ CSL 7 \ CSH 7 \ SelMod\

18 Design of address and data amplifiers 74LS LS 245 SelMod\ RD\ SA 0 SA 1 SA 7 SA 8 SA 9 SA 15 SA 16 SA 23 A0A0 A1A1 A7A7 A8A8 A9A9 A 15 A 16 A 23 SD 0 SD 1 SD 7 SD 8 SD 9 SD 15 D0D0 D1D1 D7D7 D8D8 D9D9 D 15

19 Design of a DRAM memory module