Doc.: IEEE 802.11-04/992 Submission September, 2004 Victor Stolpman et. al Irregular Structured LDPC Codes and Structured Puncturing Victor Stolpman, Nico.

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doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Irregular Structured LDPC Codes and Structured Puncturing Victor Stolpman, Nico van Waes, Tejas Bhatt, Charlie Zhang, and Amitabh Dixit This presentation accompanies submission IEEE /948

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Overview LDPC Introduction –Regular versus Irregular  Irregular codes have better performance –Structured versus Unstructured  Structured codes have better latency Irregular Structured LDPC Codes –Seed and Spreading Matrices – Building blocks for structured codes –Expanded and Exponential Matrices – LDPC code construction Simulations –BLER in AWGN  Performance improves with codeword length –Conventional BP versus Layered BP  Layered BP offers good performance with fast convergence and efficient silicon solutions –Significant performance improvement over the legacy FEC solution for both small and large packet sizes in n channels Structured Puncturing

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Low-Density Parity-Check (LDPC) Codes What is a LDPC code? –A LDPC code is simply a block code defined by a parity-check matrix that has a low density of ones (i.e. mostly zeros) –Decoding is done iteratively using Belief Propagation (BP) – passing of extrinsic information between codeword elements and parity check equations Why do you want to use LDPC codes? –Best performing forward error correction code available –Designs have approached capacity within dB –Structured designs offer the great performance with faster convergence and attractive silicon solutions –For n, structured LDPC is a viable and attractive solution with significant gains over the legacy FEC system

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Small LDPC Example Columns correspond to codeword bits Rows correspond to parity-check equations

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Regular vs. Irregular LDPC Codes Regular LDPC Codes –First developed in early 1960’s by Robert Gallager –Each column of the parity-check matrix has the same number of ones –Each row of the parity-check matrix has the same number of ones Irregular LDPC Codes –Superior performance over regular LDPC constructions –Outperform Turbo-codes – especially at high code rates! –Column-weight may vary across columns of the parity-check matrix –Row-weight may vary across rows of the parity-check matrix –Can be designed for particular channel statistics (e.g. AWGN, BEC, Rayleigh, etc.)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Unstructured vs. Structured LDPC Codes Unstructured LDPC Codes – “Random” Constructions –Randomly constructed parity-check matrix –No structure to exploit in decoding  limited decoding choices –Each codeword length requires another construction  limited block sizes or high storage requirements for multiple code lengths along with complex interconnect Structured LDPC Codes – “Architecture Aware” Constructions –Reduction of 75% or more in memory requirements! –Offers additional decoding choices that have fast convergence (e.g. Layered Belief Propagation)  high performance with low latency! –Supports many block sizes  reduction in zero-padding inefficiencies –Efficient decoder designs resulting in cheaper silicon solutions with lower power consumption and shorter interconnects

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Overview LDPC Introduction –Regular versus Irregular  Irregular codes have better performance –Structured versus Unstructured  Structured codes have better latency Irregular Structured LDPC Codes –Seed and Spreading Matrices – Building blocks for structured codes –Expanded LDPC and Exponential Matrices – Constructing a code Simulations –BLER in AWGN  Performance improves with codeword length –Conventional BP versus Layered BP  Layered BP offers good performance with fast convergence and efficient silicon solutions –Significant performance improvement over the legacy FEC solution for both small and large packet sizes in n channels Structured Puncturing

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Parity-Check “Seed” Matrix Small binary matrix  low storage costs Acts as a blueprint to the structure of the expanded LDPC code Constructed from an edge-distribution with good asymptotic properties for the desired channel (e.g. AWGN, BEC, Fading, MIMO, etc.) Expanded using permutation matrices (e.g. circular-shift matrices) to construct the LDPC code used for FEC After expansion, the final LDPC matrix will be of the same code ensemble as the seed matrix with the same asymptotic performance

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Permutation “Spread” Matrices Finite set of matrices consisting of circular-shift matrices, the identity matrix, and the all zeros matrix Act as building blocks for the expanded LDPC matrix Each is indexed using their exponent values (i.e shift-coefficients)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Expanded LDPC Matrix In matrix notation, we write “Expanded” LDPC matrix whose sub-matrices belong to Thus, the final exponents (i.e. shift-coefficients) are of the finite set:

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Universal Exponential Matrix Exponential matrix definition used for all structured LDPC codes Because it is “rule-based” and not tied to a particular “seed” matrix, it offers forward-compatibility and hardware reuse for different device classes Supports all codeword lengths and code rates without additional storage for exponent values (i.e. shift-coefficients)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Final Exponential Matrix Constructed via masking the “seed” matrix with the “universal” exponent matrix (Note: operations can be reduced to just the ones locations in the seed parity-check matrix) We mask the seed matrix with the universal exponential:

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Small Construction Example Parity Systematic

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Overview LDPC Introduction –Regular versus Irregular  Irregular codes have better performance –Structured versus Unstructured  Structured codes have better latency Irregular Structured LDPC Codes –Seed and Spreading Matrices – Building blocks for structured codes –Expanded and Exponential Matrices – LDPC code construction Simulations –BLER in AWGN  Performance improves with codeword length –Conventional BP versus Layered BP  Layered BP offers good performance with fast convergence and efficient silicon solutions –Significant performance improvement over the legacy FEC solution for both small and large packet sizes in n channels Structured Puncturing

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al BPSK-AWGN Simulations Simulated codeword lengths: –{576,720, 768, 864, 960, 1008, 1152, 1296, 1344, 1440, 1536, 1584, 1728, 1872, 1920, 2016, 2112, 2160, 2304} –Larger codeword lengths are already supported by the specified seed matrices Permutation spreading sub-matrix dimensions: –{12,15,16,18,20,21,24,27,28,30,32,33,36,39,40,42,44,45,48} Rate 1/2 seed matrices of dimension (24x48) –3 seed matrices (all 3 from the same ensemble) Rate 2/3 seed matrices of dimension (16x48) –4 seed matrices (all 4 from the same ensemble) Rate 3/4 seed matrices of dimension (12x48) –4 Seed matrices (all 4 from the same ensemble) 50 iterations of conventional belief propagation (i.e. Sum-Product- Algorithm (SPA))

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 1/2 BLER – AWGN BPSK

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 2/3 BLER – AWGN BPSK

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 3/4 BLER – AWGN BPSK

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Layered Belief Propagation Parity-check matrix is partitioned into layers and messages are passed between Speeds convergence time significantly  High performance with low latency Significant reduction in memory requirements (75% reduction) Most structured LDPC codes can implement layered-BP in cost effective solutions

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Layered vs. Conventional BP (Rate 1/2) Layered BP (15 iterations) Conventional BP (50 iterations)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Structured LDPC, N=1920, Different Code-Rates

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Structured LDPC, N=1920, Rate 1/2

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al n Channel Simulations Channel B –2x2 MIMO with 2 spatial streams in 20MHz –30 iterations of conventional belief propagation (i.e. SPA) –Large packet sizes using concatenated codewords of length 2304 Channel D –1x1 SISO in 20MHz –20 iterations of conventional belief propagation (i.e. SPA) –Small packet sizes using a single codeword of length 2304 Channel E –2x2 MIMO with 2 spatial streams in 20MHz –30 iterations of conventional belief propagation (i.e. SPA) –Large packet sizes using concatenated codewords of length 2304

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Channel B 2x2 Simulation Results Over 3dB gain in 2x2

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Channel D 1x1 Simulation Results ~2dB Gain in 1x1

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Channel E 2x2 Simulation Results Over 3dB gain in 2x2

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Features Forward compatibility and hardware reuse –Existing seed sets already support longer codeword lengths –Additional seed are easily added for different channel models, additional code rates, and to accommodate tradeoffs in silicon “Architecture Aware” constructions that allow for Layered-BP –Fast convergence  high performance and low latency –Efficient silicon solutions Wide range of block sizes reduces zero-padding inefficiencies Upper triangular seed matrices  linear time encoding In the pipeline … –Seed matrices for additional code rates 5/6 and 7/8 –Additional seed sizes for different number of data sub-carriers (e.g 40MHz channel bonding)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Overview LDPC Introduction –Regular versus Irregular  Irregular codes have better performance –Structured versus Unstructured  Structured codes have better latency Irregular Structured LDPC Codes –Seed and Spreading Matrices – Building blocks for structured codes –Expanded and Exponential Matrices – LDPC code construction Simulations –BLER in AWGN  Performance improves with codeword length –Conventional BP versus Layered BP  Layered BP offers good performance with fast convergence and efficient silicon solutions –Significant performance improvement over the legacy FEC solution for both small and large packet sizes in n channels Structured Puncturing

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Structured Puncturing of LDPC Codes Used to offer all possible code rates in between and above the basic code rate set {1/2,2/3,3/4,7/8} Puncturing does not require changing the parity-check connective net at either the encoder or decoder Supports easy link adaptation. In MIMO applications, puncturing allows for different spatial streams to have different code rates without using multiple coding blocks Approach can be reused in Hybrid-ARQ systems Structured approach reduces storage requirements and expands easily to multiple block lengths

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al “Seed” Degree Puncture Sequence Vector containing the variable-degrees corresponding to the variable-nodes of a seed parity-check matrix to be punctured. Acts as a blueprint and reduces puncture sequence storage Expanded using the Kronecker product for obtaining the variable-degrees corresponding to the variable-nodes of the expanded LDPC matrix Then, mapped to variable-nodes of the expanded LDPC matrix

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 1/2 Puncture Example (Mother Code, N=624)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 2/3 Puncture Example (Mother Code, N=2318)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Rate 3/4 Puncture Example (Mother Code, N=2352)

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al Summary Irregular Structured LDPC codes have great performance Offers forward-compatibility and hardware reuse Already supports codeword lengths greater than 2304 “Architecture Aware” constructions  Layered-BP decoding Efficient silicon solutions with high throughput and low latency Wide range of block sizes reduces zero-padding inefficiencies Upper triangular seed matrices  linear time encoding Structured puncturing allows for additional code rates for use with spatial stream adaptation in MIMO systems

doc.: IEEE /992 Submission September, 2004 Victor Stolpman et. al References 1.T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, “Design of Capacity Approaching Irregular Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 47, pp , Feb Sae-Young Chung, On the Construction of Some Capacity-Approaching Coding Schemes, PhD Dissertation, MIT, J. Hou, P. Siegel, and L Milstein, “Performance Analysis and Code Optimization of Low Density Parity-Check Codes on Rayleigh Fading Channels,” IEEE J. Select. Areas Commun., Issue on The Turbo Principle: From Theory to Practice I, vol. 19, no. 5, pp , May M. M. Masour and N. R. Shanbhag, “Turbo decoder architectures for low-density parity check codes,” IEEE Global Comm. Conf. (GLOBECOM), Nov. 2002, pp M. M. Mansour and N. R. Shanbhag, “Low power VLSI architectures for LDPC codes,” in 2002 International Low Power Electronics and Design, 2002, pp D. E. Hocevar, “LDPC code construction with flexible hardware implementation,” Proc.: IEEE Int’l Conf. On Comm. (ICC), Anchorage, AK, May M. M. Mansour and N. R. Shanbhag, “High-Throughput LDPC Decoders,” IEEE Trans. On VLSI Systems, vol. 11, No. 6, pp , December 2003.