Matrix Multiplication on FPGA Final presentation One semester – winter 2014/15 By : Dana Abergel and Alex Fonariov Supervisor : Mony Orbach High Speed Digital System Laboratory

Motivation and Background Matrix multiplication is a complex mathematical operation. Naive implementation of the common algorithm may cost a lot of resources and time. An efficient matrix multiplication implementation is needed.

Project Goals Implementation of an efficient algorithm and Infrastructure Minimum FPGA resources. Minimum run time. Maximum throughput Examine the trade off Working with memory interfaces (DDR)

Development Platform VHDL Simulation – ModelSim/Vivado Xillinx – vc709 Evaluation Board FPGA - Virtex 7 Synthesis - Vivado

Algorithm and Specifications

Block Diagram Two time domains. Read FIFO: write width- 512bit read width- 1024bit Write FIFO: write width- 64bit read width- 32bit

Consist of 129 multipliers. Multiplier’s input width is 8 bit. Multiplier’s output width is 16 bit. The multipliers are DSP slices. An additional multiplier for the valid bit.

Consists of 127 adders. The adder’s width increases by 1 as the data advances through the pipeline. Pipeline implementation.

DDR_Interconnect (IP Integrator) Contains the following IP’s: Axi_data_mover Axi_interconnect mig

Memory Organization

Flow Chart

Design Verification BIST (Built-In Self Test) Memory tests (C code of the microblaze) were adjusted to our purposes: Loading the matrixes to the DDR. Reading the result matrix from the DDR.

Verification Process Three bit-stream files are involved in the process: 1.Bist that was modified to write the matrixes to the DDRs. 2.Our design, which reads the matrixes, does the arithmetic calculation and writes the result matrix to the DDR. 3.Bist that was modified to read the result matrix and print it on the screen.

Performance Total run time: 1.1 sec (220,940,637 clock cycles in 200 Mhz) Throughput: Total FPGA utilization:

Summery and conclusions

Thank you!