Lecture 3. RAS Issues in Lucida Prof. Taeweon Suh Computer Science Education Korea University COM609 Topics in Embedded Systems.

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Lecture 3. RAS Issues in Lucida Prof. Taeweon Suh Computer Science Education Korea University COM609 Topics in Embedded Systems

Korea Univ Return Address Stack Issues in Lucida Push and Pop timing  Push the return address in ID stage? What if the conditional branch turns out to be predicted wrong? Corrupt RAS  Pop from RAS in IF stage? Need to decode the return instruction in IF stage: JPLR (Jump to Link Register), POP PC, JR ? Unmatched call/return sequences  What if the conditional branch turns out to be predicted wrong? Corrupt RAS  Exception or Interrupt What is the instruction for returning from interrupt? (SR restore)  Context Switch Timer interrupt  Clear RAS at the reception of interrupt or exception?  longjmp() / setjump() ? Misprediction detection and correction logic 2

Korea Univ Basic Operation in Lucida 8-entry RAS? RAS reset conditions,  Overflow/Underflow  Unmatched sequence Or use circular buffer and let it overflow or underflow? If the RAS return is wrong, then reset the RAS.. 3

Korea Univ RAS Corruption due to Conditional Branch Misprediction No corruption because the conditional branch is resolved in ID stage  If the speculated instruction is jlr -kind instruction, it will be squashed immediately because it is in IF stage, assuming that jlr -kind inst. pushes the return address in ID stage 4

Korea Univ RAS Corruption due to RAS Misprediction It could come from unmatched sequence (jal, jalr) – (jplr, jr?) pair  We don’t consider jr  jplr is resolved in ID stage. No problem in case of the misprediction. The same reason as the conditional branch misprediction pop pc is resolved in MEM stage. Then, what if the prediction was wrong? There are 3 instructions in the pipe after POP PC  We almost decided to use the normal stack-like structure (not the one in Patt’s paper)  Checkpoint TOS and NEXT (Patt’s paper) at each prediction with RAS? Need at most 2-3 buffers RAS reset conditions? 5

Korea Univ Misc We don’t take the following cases into account in RTL design since it would occur extremely rarely (Make common cases faster!)  JAL, JPLR : immediately return from subroutine It could corrupt the instruction queue since RAS push from JAL occurs in ID stage? Then IQ could be filled with instructions from wrong path? I am not quite sure… 6

Korea Univ Nelahem Case Study 16-entry Return Stack Buffer 7

Korea Univ General Lucida Questions What happens in IF stage when the conditional branch is turned out to be mis-predicted? When executing jal, jalr instructions, the return address is saved in ID stage? 8