Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 1 Production Readiness Review of the MDT ROD Electronic Design Details

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 2 MROD-X Design, Changes with respect to the MROD-1 design MROD-1MROD-X 3x + SHARC links used for data transport RocketIO links used for data transport

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 3 MROD-Out FPGA Rocket IO RocketIO between MROD-In and MOD-Out FPGAs MROD-In FPGA Rocket IO FIFO Gb/s (160 MB/s) FIFO 511 FIFO 511 FIFO 511 Regis- ters FIFO 511 HF Extended Return Data Event Data Event Length (+ID) Event Data Event Length (+ID) Return Data FIFO 511 RdRq Regis- ters Extended Return Data Return Data High Priority Path Low Priority Path Connections from other 7 MROD-In FPGAs Backpressure 8B/10B Extended Data Length Look-ahead TDC Limit

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 4 D5D5 D4D4 TDC Limit Register D1D1 D2D2 D3D3 DnDn BOTBOT EOTEOT } 12 bit, programmable 1 to 4096 data words TDC Word Count bits [11:0] Example when limit is set to 4: D1D1 D2D2 D3D3 BOTBOT n EOTEOT 6 D4D4 D1D1 D2D2 D3D3 BOTBOT EOTEOT 7 Register default = 0x60 Maximum Event Fragment for 18 TDCs: 18 x (BOT EOT) = 1782 words D4D4 D1D1 D2D2 D3D3 BOTBOT EOTEOT 6 D4D4 D1D1 D2D2 D3D3 BOTBOT EOTEOT 7 MROD-Out, Event Builder: Maximum Event Fragment 8 x ( envelope words) = words No shutdown as with “Maximum Event Length” (Default 1K words)

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 5 Backpressure and ROD-Busy MROD-In Buffer Memory Partition CSM link RocketIO FIFOs S-Link FIFO Link FIFO Full Half Full Almost Full X ROD-Busy Backplane P3 -> TIM Front panel NIM Front panel Led 18x 8k 8x 8K 1x 511 When one of 18 partitions Half Full Or I2O-FIFO Half Full then CSM Link Busy Front panel Led “B” I2O FIFO 512 Half Full MROD-In Buffer Memory Partition = 8K words Consider the situation where a lot of small events are received. Buffer Memory Partition does not get Half Full while I2O-FIFO rapidly fills. I2O FIFO Half Full signals ROD-Busy. UpUp B usy E rror I2O-FIFO: event fragment complete -> start MROD-In Output Controller

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 6 MROD-Out FPGA TTC FIFOs Event/Bunch-ID FIFO 511 Trigger-Type FIFO 511 MROD-Out SHARC DMA Event/Bunch-ID FIFO 511 Trigger-Type FIFO 511 Event Builder ROD-Busy Backplane P3 -> TIM Front panel NIM Front panel Led HF TTC1 ECR TTC4 Event/ Bunch-ID TTC5 Trigger Type De Serialize De Serialize Extended Event-ID Inc Load P3 backplane driven by TIM Debug Test Monitor Other busy sources

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 7 Event Builder (1) Event Data Event Length Event Data Event Length 8 x TTC FIFOs not empty RocketIO 1A RocketIO 4B 1A Busy 4B Busy Channel Enable Register ROD-Busy Event Builder Test Mode Test Count Event-ID Event Fragment Trailer Event Fragment Header 4 1.Wait for TTC info 2.Send Header 3.Repeat If a channel is enabled (wait for / read) event length entry then read event data and insert Link Word Count 4.Until all channels read 5.Send Trailer

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 8 Event Builder (2) Event Fragment Header BOF (S-Link Control Word) 0xB0F00000 Header Marker 0xEE1234EE Header Size 0x Format Version Number (VME register) 0x Module ID (VME Register) 0x Run number (VME Register) 0x Event –ID 0xEEeeeeee Bunch-ID 0x00000bbb Trigger-Type 0x000000tt Detector Event Type (VME Register) 0x MROD BOB 0x80eeeeee Test Mode Normal Running eeeeee = from TTC Test Mode (run without TTC) eeeeee = from Test Counter Event Fragment Trailer MROD EOB 0xF000wwww MROD Status word (MSE1) Number of Status Elements (NSE) 0x Number of Data Elements (NDE) 0x0000wwww Status Block Position 0x EOF (S-Link Control Word) 0xE0F GOL Parity Error TDC Parity Error TDC Bunch-ID Miss Match TDC Event-ID Miss Match

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 9 Spy (MROD-In) SHARC Debug Test Monitor Event Data FIFO 512 Event Length FIFO 16 MROD-In FPGA Rocket IO Event Data FIFO 8191 Event Length FIFO 511 MROD-In Output Controller 1.MROD-X Mode 2.MROD-1 Mode 3.MROD-X Debug Spy Pre-scale register a.No b.All c.One in ‘n’ [ ] AF By Default: Main data stream is not halted by Spy Channel

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 10 Spy (MROD-Out) SHARC Debug Test Monitor Event Data FIFO 16K Event Length FIFO 4 MROD-Out FPGA Event Builder 1.MROD-X Mode 2.MROD-1 Mode 3.MROD-X Debug Spy Pre-scale register a.No b.All c.One in ‘n’ [ ] S-Link FIFO 511 AF By Default: Main data stream is not halted by Spy Channel

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 11 Test Generator MROD-In SFP SHARC FPGA Test FIFO (Pre-scaled) Data and Event-Length MROD_In Functionality External Loop back RocketIO SHARC Links TTC L1A CSM links unidirectional Test generator Transparent / Circular mode Free running / Triggered Internal test mode SFP FPGA Test FIFO (Pre-scaled) Data and Event-Length MROD_In Functionality RocketIO

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 12 XCF08P Xilinx XC2VP20 ASP FPGA_TDO MROD-Out MROD-In FPGAs J26 SelSharcF for 3 or 4 MROD-Ins TDITDO FPGA_TDI MRO_XCF08P_TDI FPGA_TDO3 FPGA_TDO4 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Xilinx XC2VP7/20 Configuration Bus Configuration Bus Remote Configuration (1) FPGA JTAG Chain MTM bus Geographical Address

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 13 Remote Configuration (2) buffers P2 P1 P3 buffers rearfront VME bus to all MROD modules MTM bus USB-JTAG (= Xilinx Download Cable)

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 14 Other Extras Year Month 15-8 Date 7-0 Revision FPGA firmware Date and Revision Register Automatically determined during synthesis of VHDL code (TCL script) OS DateRev. File ID[31-0] Unique Identifier Registers (DS2401) Family-IDCRCID[47-32] ID1 ID2 S-Link Flush Mode Temperature Readout for each FPGA (MAX 1618) Zero Suppress Override choose to override zero suppression: –Never –Once every ‘n’ [ ] events (first event of a run always non zero suppressed)

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 15 Production Readiness Review of the MDT ROD Prototype issues

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 16 Design issues found in prototypes Parallel termination for MROD-In FPGA configuration bus Pull-up resistor on FPGA TDO Wrong polarity for two capacitors Small errors in silkscreen (Dip switch SW9, Ref. IC511, Pin 1 marking) Footprint for inductors too small Short pin 1-2 for SMD LEDs (2 = Anode, 3 = Cathode) Power On Reset circuit: TPS3838 SOT Rst_n pin 4 MR pin 3 VDD pin 1,5 Critical Ramp-Rate ~ 125 mV/ms Happens to be exactly VME crate power supply Ramp-Rate! Okay Fail

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 17 Minor Assembly issues found in prototypes One capacitor misplaced (module 1) Software Test Procedure found 2 open address pins on a Temperature Sensor (module 1) One wrong component placed. IC511 = NC7SZ125 instead of NC7SZ126 (module 3) One IC557 missing (NC7SZ08) (module 5) One wrong component placed. IC564 = NC7SZ08 instead of NC7SZ126 (module 5) Open output pin on buffer, SHARC JTAG chain (module 6) Keep in mind that we asked for assembly of 6 modules (4 different production runs): 2 eight-channel, 1 eight-channel, 1 eight-channel without SHARC-B, 2 six-channel Assembly house did a great job. Some issues: Automatic Optical Inspection would track many, if not all of these failures.

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 18 Changes to be made in PCB Needed: Parallel termination for MROD-In FPGA configuration bus (add 18 resistors) Add Pull-up resistor to FPGA TDO Change the polarity for two capacitors Connect pin 1 and 2 for SOT23 SMD LEDs Increase Footprint for inductors Power On Reset (still under investigation… Use MAX 6863?) Needed for 50 MHz: Review Clock circuit on MROD-Out: –Remove automatic Clock switch for selection of LHC-Clock or crystal –Re-route one LHC-Clock signal –MROD-Out FPGA prepared, system operation still to be demonstrated Desirable: Inverter for GA[4..0] connected to ASP Review silkscreen (SW9 and IC511, Pin 1 marking)

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 19 Thank you

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 20 MROD_In SFP SHARC LHC_Clk1 MROD_In LHC_CLk2 MROD_In LHC_Clk3 MROD_In LHC_Clk4 MROD_Out SHARC B SHARC A MROD-X Clocks SFP Xilinx XC2VP7/20 Xilinx XC2VP7/20 50/8080 GOL_XClkA GOL_XClkB Rocket XClkB Rocket XClkA 40 Robo Clock ChA_Clk ChA_Clkx2 Sharc Clk ChB_Clk ChB_Clkx2 Xilinx XC2VP Rocket XClk Clk Sharc Clk Clkx2 LHC_Clk S-Link ZBT Robo Clock Robo Clock LHC_Clk (From TIM)

Peter JansweijerMROD Production Readiness Review: November 2, 2005Slide 21 MROD_In SFP SHARC MROD_In MROD_Out MROD-X Clocks 50 MHz) SFP Xilinx XC2VP7/20 Xilinx XC2VP7/20 50/ Robo Clock Xilinx XC2VP20 LHC_Clk (From TIM) ZBT Robo Clock Robo Clock X LHC_Clk1 LHC_CLk2 LHC_Clk3 LHC_Clk4 GOL_XClkA GOL_XClkB Rocket XClkB Rocket XClkA ChA_Clk ChA_Clkx2 Sharc Clk ChB_Clk ChB_Clkx2 Rocket XClk Clk Clkx2 LHC_Clk SHARC B SHARC A Sharc Clk S-Link