RT level combinational blocks Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)

Slides:



Advertisements
Similar presentations
컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley.
Advertisements

Princess Sumaya University
Modular Combinational Logic
ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School.
Class Exercise 1A.
Speical purpose Encoders/Comparators
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
CPT 310 Logic and Computer Design Instructor: David LublinerPhone Engineering Technology Dept.Cell
Homework Reading Machine Projects Labs
CPEN Digital System Design Chapter 9 – Computer Design
Chapter 7 - Part 2 1 CPEN Digital System Design Chapter 7 – Registers and Register Transfers Part 2 – Counters, Register Cells, Buses, & Serial Operations.
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Chapter 4 Register Transfer and Microoperations
Adders, subtractors, ALUs
CS 105 Digital Logic Design
Calculator Lab Overview Note: Slides Updated 10/8/12
Logic level sequential blocks Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
Combinational Circuits Chapter 3 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.
Logic Design CS221 1 st Term combinational circuits Cairo University Faculty of Computers and Information.
Outline Analysis of Combinational Circuits Signed Number Arithmetic
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.
+ CS 325: CS Hardware and Software Organization and Architecture Combinational Circuits 1.
Digital Arithmetic and Arithmetic Circuits
MSI Devices M. Mano & C. Kime: Logic and Computer Design Fundamentals (Chapter 5) Dr. Costas Kyriacou and Dr. Konstantinos Tatas ACOE161 - Digital Logic.
Chapter 4 – Arithmetic Functions and HDLs Logic and Computer Design Fundamentals.
Documentation Standards Circuit specification. –Description of what the system is supposed to do, including a description of all inputs and outputs and.
Chapter 6-1 ALU, Adder and Subtractor
ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs.
An Introduction to Digital Systems Simulation Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
ECE 545—Digital System Design with VHDL Lecture 3
Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
Digital networks classification Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit
Combinational Design, Part 3: Functional Blocks
1 CPSC3850 Adders and Simple ALUs Simple Adders Figures 10.1/10.2 Binary half-adder (HA) and full-adder (FA). Digit-set interpretation: {0, 1}
Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP
L26 – Datapath ALU implementation
Chap 7. Register Transfers and Datapaths. 7.1 Datapaths and Operations Two types of modules of digital systems –Datapath perform data-processing operations.
ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors,
Karnaugh map covering Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
Basic Boolean Functions Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
Computer Organization CS224 Fall 2012 Lesson 22. The Big Picture  The Five Classic Components of a Computer  Chapter 4 Topic: Processor Design Control.
CS 105 DIGITAL LOGIC DESIGN Chapter 4 Combinational Logic 1.
1 Chapter 4 Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables,
Computing Machinery Chapter 3: Combinational Circuits.
1 Fundamentals of Computer Science Combinational Circuits.
1 ECE 545—Digital System Design with VHDL Lecture 1 Digital Logic Refresher Part A – Combinational Logic Building Blocks.
1 Combinational Logic EE 208 – Logic Design Chapter 4 Sohaib Majzoub.
CSI-2111 Structure of Computers Ipage Combinational Circuits  Objectives : To recognize the principal types of combinational circuits  Adders.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
George Mason University Class Exercise 1B. 2ECE 448 – FPGA and ASIC Design with VHDL Rules If you believe that you know a correct answer, please raise.
ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs.
1 The ALU l ALU includes combinational logic. –Combinational logic  a change in inputs directly causes a change in output, after a characteristic delay.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
Combinational Circuits
Chap 7. Register Transfers and Datapaths
Homework Reading Machine Projects Labs
Combinational Logic Circuits
Basics of digital systems
Combinational Logic Circuits
EEL 3705 / 3705L Digital Logic Design
Combinatorial Logic Design Practices
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.
Homework Reading Machine Projects Labs
COMS 361 Computer Organization
Logic Circuits I Lecture 3.
Combinational Circuits
Arithmetic Circuits.
Presentation transcript:

RT level combinational blocks Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Lecture 5.1

2 5.1 Goal  This lecture presents the set of functional blocks that are usually considered to be “elementary” or “basic” at the RT level.

3 5.1 Prerequisites  Lecture 3.3

4 5.1 Homework  No particular homework is foreseen

5 5.1 Further readings  Students interested in making a reference to a text book on the arguments covered in this lecture can refer, for instance, to:  M. Morris Mano, C.R.Kime: “Logic and Computer Design Fundamentals,” 2nd edition updated Prentice Hall, Upple Saddle River, NJ (USA), 2001, (chapter 3, pp )

6 5.1 Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

7 5.1 Adders We shall consider:  half adder  full adder  adder-subtracter

8 5.1 Half-Adder A half-adder has:  2 inputs A i, B i  2 outputs S i and C i+1 and computes the binary sum of the 2 input bits, providing:  the sum S i  the carry C i+1

9 5.1 S i = A i  B i C i+1 = A i  B i A i B i C i+1 S i

Full-Adder A full-adder has:  3 inputs A i, B i and C i  2 outputs S i and C i+1 and computes the binary sum of the 3 input bits, providing:  the sum S i  the carry C i+1

S i = A i  B i  C i C i+1 = A i B i + A i C i + B i C i = = A i B i + ( A i  B i ) C i  A i B i C i C i+1 S i

Adder-subtracter An adder-subtracter is a combinational block capable of adding/subtracting two n-bits inputs operands, detecting overflow conditions. It has  2 n-bits data inputs, both labeled from n-1 to 0  1 control input to select one of the two operations  1 n-bits data output  1 control output asserted when an overflow condition is occurred.

Adder-subtracter Adder-subtracter (cont’d) FUNC(n-1 downto 0) A(n-1 downto 0) B(n-1 downto 0) ADD/~SUB OVFL Symbol

Elementary functional blocks Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces Multiplexer

Multiplexer A multiplexer is a combinational block capable of forcing its output to the current value of one of its inputs, according to the values of some control signals. Each input can be either a single wire or a bus.

Multiplexer A multiplexer has:  2 k data inputs, labeled from 2 k -1 to 0  k control inputs  1 data output. k 2 k -1 2 k MUX … It gets the value present on the input labeled 2 i, where i (0  i  k-1) is the binary number present on the control inputs.

OUT SEL(k-1 downto 0) Multiplexer (cont'd) Symbol IN(2 k -1 downto 0)

Multiplexer (cont’d) Symbol M0(n-1 downto 0) OUT(n-1 downto 0) M1(n-1 downto 0) M2(n-1 downto 0) M2 k -1(n-1 downto 0) SEL(k-1 downto 0)

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

Decoder A decoder k  2 k has:  1 n-bit data input  2 n outputs, labeled from 0 to 2 n -1  1 enable. When enabled, just the output labeled 2 j is active, where j is the value present on the data input. When disabled, no output is active.

Decoder (cont’d) Symbol DOUT(0) DIN(n-1 downto 0) ENABLE DOUT(1) DOUT(2) DOUT(2 n -1)

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

Priority Encoder A priority encoder has:  2 k inputs, labeled from 0 to 2 k -1 (each input is assigned a fixed priority)  k outputs  1 “data valid” output  1 enable.

Priority Encoder (cont’d)  When enabled:  the outputs get the value j, where j is the label of the highest priority asserted input  the “data valid” output is asserted.  When disabled or when no input is asserted:  the “data valid” output is not asserted.

M0 CODE(n-1 downto 0) ENABLE M1 M2 M2 n -1 Priority Encoder (cont’d) VALID Symbol

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

Comparator A comparator gets 2 n-bit binary numbers:  A(n-1 downto 0)  B(n-1 downto 0) and provides in output the result of the comparison between A and B. A control input UM/~2C specifies whether the input operands are unsigned or signed, respectively.

Comparator (cont’d) A B AeqBAneBAltBAgtBAleBAgeB Symbol B(n-1 downto 0) A(n-1 downto 0) UM/~2C Sel

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

Counter of 1’s occurrences A counter of 1’s occurrences has:  1 n-bit data input  1 m-bit data output, being m =  log 2 n . The device counts the number of occurrences of a ‘1’ on its inputs and provides it on its outputs.

Counter of 1’s occurrences Counter of 1’s occurrences (cont’d) Symbol DIN(n-1 downto 0) 1’s C DOUT(m-1 downto 0)

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

ROM A 2 k  n ROM (Read-Only Memory) has:  k address inputs  n data outputs  2 k n-bit internal cells, storing permanent values. The outputs gets the value stored in the j cell, j being the current value present on address inputs.

ROM (cont’d) ADDR D_OUT Symbol ADDR(2 k -1 downto 0) DATA(n-1 downto 0)

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

ALU An n-bit ALU (Arithmetic Logic Unit) performs logic and/or arithmetic operations on 2 n-bit operands, under the control of ad-hoc control signals.

ALU (cont’d) FUNC(n-1 downto 0) CONTROL C_IN C_OUT STATUS Symbol B(n-1 downto 0) A(n-1 downto 0)

F=A  B F=A  B' Functions implemented by the ALU ’181 InputFunctions S3S2S1S0arithmetic (M=0)logic (M=1) F=A minus 1 plus CIN F=AB minus 1 plus CIN F=AB' minus 1 plus CIN F=1111 plus CIN F=A plus (A+B') plus CIN F=AB plus (A+B') plus CIN F=A minus B minus 1 plus CIN F=A+B' plus CIN F=A plus (A+B) plus CIN F=A plus B plus CIN F=AB' plus (A+B) plus CIN F=A+B plus CIN F=A plus A plus CIN F=AB plus A plus CIN F=AB' plus A plus CIN F=A plus CIN F=A' F=A'+ B' F=A'+ B F= 1111 F=A'B' F=B' F=A+B' F=A'B F=B F=A+B F=0000 F=AB' F=AB F=A

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

Multiplier A multiplier has:  1 n-bits data inputs, labeled from n-1 to 0  1 m-bits data inputs, labeled from m-1 to 0  no control signals  k-bits data outputs, labeled from k-1 to 0 and provides in output the results of the product between the two input operands.

Multiplier (cont’d) MUL_OUT(k-1 downto 0) * B(n-1 downto 0) A(m-1 downto 0) Symbol

Multiplier (cont’d) MUL_OUT(k-1 downto 0) * B(n-1 downto 0) A(m-1 downto 0) Symbol Signed operands: k=m+n- 1Signed operands: k=m+n- 1 Unsigned operands: k=m+nUnsigned operands: k=m+n

Elementary functional blocks Multiplexer Adder- Subtracter Decoder Encoder Comparator ROM ALU Multiplier 1’s counter I/O interfaces

I/O interfaces The combinational interfaces for the following I/O devices will be presented:  led bar driver  7-segments display  dip-switch  keypad.

Led bar interface LED_BAR interface n DATA(n-1 downto 0)

DATA DISPLAY interface 4, 7 DOT ENABLE 7-segments display interface

a b c d e f g BI A B C D a b c d e f g a b c d e f g DOT ENABLE 7-segments display interface

Dip-switch interface DATA DIP_SW interface n n

Keypad interface DATA KEYPAD interface 4, AB CDEF DATA_VALID