1 Lab7 Design and Implementation

2 Design Example : Parity checker

3 Computer to Spartan-6 USB Port Spartan-6 PC

4 DIP SWITCHES & LEDs DIP SWITCH LED

5 Power to Board 變壓 整流器 AC 110V DC 5V

6 Create a New Project

7 Enter a Name and Location for the Project 檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名

8 Select Device Family, Package, Device and Speed Grade 1 2

9 Finish

10 Create a New File 1.Right Click 2

11 Create a New Module 1 2. Type “ logic ”

12 Define I/O Port 1.Type x,y,z,f 2.Select I/O

13 Finish

14 Type 1.Type 2.Remember to save the file

Check Synthesize 2.Double Click 1.Double Click

16 Add Verilog Test Fixture 1.Right Click 檔名開頭請勿使用數字或特殊符號 並不要使用中文為檔名

17 Finish 1 2

Test bench Remember to save the file

Generate Expected Simulation Result Double Click

20 Click Zoom Full 1.Run all2.Click

21 Result f=x^y ^z

Enter the PlanAhead Double Click

23 Pins Assign User I/O FPGA Pin Signal LED1  E13  f Sw1  D14  x Sw2  E12  y Sw3  F12  z

24 Assign pins [1] key in 4

25 Assign pins [2] key in

26 Assign pins [3] key in

27 Assign pins [4] key in 4. Save

It’s Generate by PlanAhead 28 1.Double Click 2.

29 Run “ Implement Design ” 1 2. Double Click

30 Select FPGA Start-Up Clock to JTAG Clock 1. Right Click

31 Generate Bitstream File Double Click

32 Run “ Configure Device ” Double Click 此時請務必將版子接上

Create a New Project on ISE iMPACT

34 Select Boundary.. and Automatically … 2 1

35 Select “ logic.bit file ” 1.Double click 2

Press “ok” 36

37 Right-click to select operation 2 1.Right Click

38 Program Succeeded Check the Result on spartan-6

39 Check the Result on spartan-6 DIP SWITCH LED

40 Question and Answer 歷史人物中，誰跑最快 ?