© 2000 Morgan Kaufman Overheads for Computers as Components System components zTiming diagrams. zMemory. zBusses and interconnect.

© 2000 Morgan Kaufman Overheads for Computers as Components Timing diagrams zA timing diagram shows a trace through the operation of a system. yGenerally used for asynchronous machines with timing constraints. enq ack

© 2000 Morgan Kaufman Overheads for Computers as Components Timing diagram syntax zConstant value: zStable: zChanging: zUnknown: 0 1

© 2000 Morgan Kaufman Overheads for Computers as Components Timing constraints zMinimum time between two events: enq ack 20 ns

© 2000 Morgan Kaufman Overheads for Computers as Components Origin of timing constraints zControl signals are passed on the bus: a 20 ns c DQ

© 2000 Morgan Kaufman Overheads for Computers as Components Memory device organization Memory array n r c

© 2000 Morgan Kaufman Overheads for Computers as Components Memory parameters zSize. yAddress width. zAspect ratio. yData width.

© 2000 Morgan Kaufman Overheads for Computers as Components Types of memory zROM: yMask-programmable. yFlash programmable. zRAM: yDRAM. ySRAM.

© 2000 Morgan Kaufman Overheads for Computers as Components SRAM vs. DRAM zSRAM: yFaster. yEasier to integrate with logic. yHigher power consumption. zDRAM: yDenser. yMust be refreshed.

© 2000 Morgan Kaufman Overheads for Computers as Components Typical generic SRAM SRAM CE’ R/W’ Adrs Data

© 2000 Morgan Kaufman Overheads for Computers as Components Generic SRAM timing time CE’ R/W’ Adrs Data readwrite From SRAMFrom CPU

© 2000 Morgan Kaufman Overheads for Computers as Components Generic DRAM device DRAM CE’ R/W’ Adrs Data RAS’ CAS’

© 2000 Morgan Kaufman Overheads for Computers as Components Generic DRAM timing time CE’ R/W’ RAS’ CAS’ Adrs Data row adrs col adrs data

© 2000 Morgan Kaufman Overheads for Computers as Components Page mode access time CE’ R/W’ RAS’ CAS’ Adrs Data row adrs col adrs data col adrs col adrs data

© 2000 Morgan Kaufman Overheads for Computers as Components RAM refresh zValue decays in approx. 1 ms. zRefresh value by reading it. yCan’t access memory during refresh. zCAS-before-RAS refresh. zHidden refresh.

© 2000 Morgan Kaufman Overheads for Computers as Components Other types of memory zExtended data out (EDO): improved page mode access. zSynchronous DRAM: clocked access for pipelining. zRambus: highly pipelined DRAM.

© 2000 Morgan Kaufman Overheads for Computers as Components Flash issues zFlash is programmed at system voltages. zErasure time is long. zMust be erased in blocks.

© 2000 Morgan Kaufman Overheads for Computers as Components Generic bus structure zAddress: zData: zControl: m c n

© 2000 Morgan Kaufman Overheads for Computers as Components Electrical bus design zBus signals are usually tri-stated. zAddress and data lines may be multiplexed. zEvery device on the bus must be able to drive the maximum bus load: yBus wires. yOther bus devices. zBus may include clock signal. yTiming is relative to clock.

© 2000 Morgan Kaufman Overheads for Computers as Components Four-cycle handshake enq ack 4 1 data 2 3

© 2000 Morgan Kaufman Overheads for Computers as Components Busses as communicating machines enq = 1 enq = M1 ack = 0 ack = M2 ack enq

© 2000 Morgan Kaufman Overheads for Computers as Components When should you handshake? zWhen response time cannot be guaranteed in advance: yData-dependent delay. yComponent variations.

© 2000 Morgan Kaufman Overheads for Computers as Components Fixed-delay memory access CPU memory R/W data = mem[adrs] R W mem[adrs] = data R/W data adrs read = 1 adrs = A reg = data

© 2000 Morgan Kaufman Overheads for Computers as Components Variable-delay memory access CPU memory read = 1 adrs = A reg = data R/W done = 0 data = mem[adrs] done = 1 mem[adrs] = data done = 1 R W R/W data adrs done y n

© 2000 Morgan Kaufman Overheads for Computers as Components Typical bus access time clock R/W’ Address enable adrs Data Ready’ data read write

© 2000 Morgan Kaufman Overheads for Computers as Components Bus mastership zBus master controls operations on the bus. zCPU is default bus master. zOther devices may request bus mastership. ySeparate set of handshaking lines. yCPU can’t use bus when it is not master.

© 2000 Morgan Kaufman Overheads for Computers as Components Direct memory access (DMA) zDMA provides parallelism on bus by controlling transfers without CPU. CPU memory I/O DMA

© 2000 Morgan Kaufman Overheads for Computers as Components DMA operation zCPU sets up DMA transfer: yStart address. yLength. yTransfer block length. yStyle of transfer. zDMA controller performs transfer, signals when done: yCycle-stealing. yPriority.

© 2000 Morgan Kaufman Overheads for Computers as Components PowerPC busses

© 2000 Morgan Kaufman Overheads for Computers as Components USB 2.0 zGoals: yEasy to use. yLow cost for consumer devices. yUp to 480 Mb/s. yReal-time audio, video. yBoth isochronous and asynchronous communication.

© 2000 Morgan Kaufman Overheads for Computers as Components USB architecture host device interconnect Bus topology. Stack. Data flow model. Schedule.

© 2000 Morgan Kaufman Overheads for Computers as Components Bus tiers host function hub function Tier 1 tier 2 tier 3 tier 4 …. tier 7 Device = {hub, function}

© 2000 Morgan Kaufman Overheads for Computers as Components USB signaling zSpeeds: yHigh-speed is 480 Mb/s. yFull-speed is 12 Mb/s. yLow-speed is 1.5 Mb/s. zSignals: yVbus, Gnd. yD+, D-.

© 2000 Morgan Kaufman Overheads for Computers as Components USB power zUSB devices can pull a limited amount of power from the bus. yMay also supply their own power. zSystem may provide a power- management protocol. yIndependent of USB.

© 2000 Morgan Kaufman Overheads for Computers as Components USB bus protocol zPolled bus, all transfers initiated by host. zBasic transaction: yHost sends token packet: xType and direction. xUSB device number. xEndpoint number (subdevice). yData transfer packet. yAcknowledge packet.

© 2000 Morgan Kaufman Overheads for Computers as Components Robustness zError detection/correction. zAutomatic handling of device attach/detach. zSelf-recovery in protocol. zStreaming data management. zPipes for data management.

© 2000 Morgan Kaufman Overheads for Computers as Components USB pipes zFunctions are allocated to data pipes. yPipes limit interference between functions. zBandwidth is allocated among pipes. zDevices must supply buffer memory.

© 2000 Morgan Kaufman Overheads for Computers as Components USB data flow model zFour types of implementation: yDevice hardware. yClient software to connect to application. yUSB system software. yUSB host controller (host side system interface). hostdevice Client SW USB system SW USB host controller function USB logical device USB bus interface Physical communication

© 2000 Morgan Kaufman Overheads for Computers as Components Logical bus topology zBus appears to be a simple host/device system: host device

© 2000 Morgan Kaufman Overheads for Computers as Components Client software view zEach client sees its own function but not the whole system: function Client SW function Client SW function Client SW function Client SW

© 2000 Morgan Kaufman Overheads for Computers as Components Endpoints zEach logical device is a collection of endpoints. zEach endpoint is simplex (input or output). zEndpoint description: yBus frequency/latency. yBandwidth requirement. yEndpoint number. yError handling requirements. yMaximum packet size. yTransfer type. yTransfer direction.

© 2000 Morgan Kaufman Overheads for Computers as Components Pipes zTwo types of pipes: yStream. yMessage. zPipe description includes: yPipe type. yDirection. yBus access and bandwidth.

© 2000 Morgan Kaufman Overheads for Computers as Components Bus transfer types zData goes through the pipe in FIFO order. zFour types of transfers: yControl. yIsochronous—periodic data stream. yInterrupt. yBulk—non-periodic, large data transfer.