1 Designing for 65nm and Beyond Where’s The Revolution ?!? Greg Spirakis Absolutely, positively not working for Intel (or anyone else) EDP 2005

2 The Move To SOC Designs Was A Failure Source*: Collett International Research and Synopsys 1 st Silicon Success % 44% 48% 33% Myth of Hard IP Reuse + Reliance on 20 Year Old Design Flow Failure

3 Closer Look 2,000 engineer years to write 25M lines of RTL and 1 Trillion simulation vectors to verify Gates 1M10M100M Engineer Years Engineer Years ,000B 10B 100M Simulation Vectors Simulation Vectors And It’s Going to Get Worse Source*: Synopsys

4 But Look Where We Focus DAC 2005 Session Summary  47 Paper Sessions (plus 8 panels)  9 Logic Design and Test  Error Tolerant Design  Programmable Architectures  SAT: Cool Algorithms and Hot Applications  Methods and Representations for Logic Synthesis  Advances in Synthesis  Advances in DFT Methods  Testing for Process and Timing Related Faults  New Directions in FPGA Technologies  CAD for FPGA  5 ESL  Tools and Methods for the Verification of Processors and Processor-Based Systems  Matlab(TM) -The Other Emerging System-Design Language  Application Specific Architecture Design Tools  Formally Verifying Your 10-Million Gate Design  Effective Formal Verification Using Word-level Reasoning, Bit-level Generality, and Parallelism 75% Of Respins Due To Logic Problems But… 70% Of DAC Focused On Everything Else

5 Highest Abstraction Level Product family manuals & docs What’s Wrong ? Layout polygons Schematic transistors Schematic gates Library gates Structured RTL Transistor physics Synthesizable RTL  Architecture Performance Model Abstract of “what” you will build Architectural Family Ultimately, “what” you want Layout/Schematic netlist compare Abstraction limited by logic equivalence capabilities Formal Logic Equivalence Design rule checking Less details allowing more designed functionality Abstracts of “how” you built it Lowest Abstraction Level We need a dramatic increase in design abstraction while maintaining the link to the physical implementation Need a new design paradigm to further raise the level of abstraction!!! Need a new design paradigm to further raise the level of abstraction!!!

6 The Revolution  Structured methodology that limits the space of exploration, yet achieves good results in the fixed time constraints of the design;  A formal mechanism for identifying the most critical hand-off points in the design chain;  A method for design re-use at all abstraction levels based on assembling and configuring platform components in a rapid and reliable fashion;  An intellectual framework for the complete electronic design process. A. Sangiovanni-Vincentelli, DAC June 04 Platform Based Design  Raise the level of abstraction by creating a high level model (HLM)  Successively refine the design ensuring that each refinement is equivalent to the previous one  Tightly integrate logic and physical design domains  Enable extensive use of a repository of trusted design transformations generated during the design process Integrated Design and Verification G. Spirakis, DATE Feb 04

7 Platform-based Design   Platform: An abstraction layer in the design flow that facilitates a number of possible refinements into a subsequent abstraction layer (platform) in the design flow.   Platform Stack: Every pair of platforms, the tools and methods that are used to map the upper layer of abstraction into the lower level one. A. Sangiovanni-Vincentelli Top-Down:  Define a set of abstraction layers  From specifications at a given level, select a solution (controls, components) in terms of components (Platforms) of the following layer and propagate constraints Bottom-Up:  Platform components (e.g., micro- controller, RTOS, communication primitives) at a given level are abstracted to a higher level by their functionality and a set of parameters that help guiding the solution selection process. The selection process is equivalent to a covering problem if a common semantic domain is used.

8 Integrated Design and Verification  Raise the level of abstraction by creating a high level model (HLM)  Successively refine the design ensuring that each refinement is equivalent to the previous one  Tightly integrate logic and physical design domains  Enable extensive use of a repository of trusted design transformations generated during the design process Integrated Design & Verification Ensure Final Implementation Maintains Equivalence To HLM While Meeting Design Goals

9 A higher level expressive language Visualize the code Ungroup/group, move logic to make simple optimizations An Example f LLLLLL Validation Target HLM Code Use cross domain visibility between HLM and schematic Equiv Verify transformation is correct fafa LLLLLL fbfb

10 Refine the design Replace some blocks with circuits from libReplace some blocks with circuits from lib Create new circuits and replace blocksCreate new circuits and replace blocks Synthesize other blocksSynthesize other blocks Apply trusted transformationsApply trusted transformations Determine feasibilityDetermine feasibility Equiv An Example Successive Refinement fafa LLLLLL fbfb f LLLLLL Visualize the code Ungroup/group, move logic to make simple optimizations Validation Target HLM Code Equiv fcfc LLLLLL fdfd fefef

11 fafa LLLLLL fbfb Equiv Validation Target HLM Code Equiv Refine the designRefine the design Replace some blks with circuits from libReplace some blks with circuits from lib Create new circuits and replace blocksCreate new circuits and replace blocks Synthesize other blocksSynthesize other blocks Apply trusted transformationsApply trusted transformations Determine feasibilityDetermine feasibility f LLLLLL Visualize the code Ungroup/group, move logic to make simple optimizations fcfc LLLLLL fdfd fefef An Example Further Design Refinement flfl L fgfg L fhfh L fifi L fjfj L fkfk L Many Iterations Iteratively, further refine the design Replace some blocks with circuits from libReplace some blocks with circuits from lib Create new circuits and replace blocksCreate new circuits and replace blocks Synthesize other blocksSynthesize other blocks Apply trusted transformationsApply trusted transformations Determine feasibilityDetermine feasibility Equiv Today’s Netlist Final Netlist equivalent to HLM !!!

12 Key Is To Keep Track Of Every Step RefinementTransformation Start with a small block of the design CircuitLibUse Becomes a “Trusted” Transformation Transf.LibAdd Refine to next level Formally Verify Document every design change (transformation) Use cross-domain visibility to estimate impact on other domains impact on other domains Analyze

13 Add Build And Use Design IP Repository Store Every New Circuit And Trusted Transformation X X XX X Transf.LibUseCircuitLibUse Add X Does not meet timing ! Does not meet power ! Add to the circuit lib X Does not meet area ! Does not meet testability !

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15 The Revolution Platform Based Design  Structured methodology that limits the space of exploration, yet achieves good results in the fixed time constraints of the design;  A formal mechanism for identifying the most critical hand-off points in the design chain;  A method for design re-use at all abstraction levels based on assembling and configuring platform components in a rapid and reliable fashion;  An intellectual framework for the complete electronic design process.  Raise the level of abstraction by creating a high level model (HLM)  Successively refine the design ensuring that each refinement is equivalent to the previous one  Tightly integrate logic and physical design domains  Enable extensive use of a repository of trusted design transformations generated during the design process Integrated Design and Verification A. Sangiovanni-Vincentelli, DAC June 04G. Spirakis, DATE Feb 04 Transform Intractable CAD Engineering Problem Into Tractable SW Engineering Problem

16 Next Steps/Call to Action  New design flow based on Platform Based Design and IDV concepts must be developed  EDA industry must restructure its investment to embrace the new paradigm  Academia MUST lead this effort and make it THE design flow at all universities This is a Design Flow and SW Engineering problem NOT a traditional EDA problem