A New High Speed, Low Power Adder; Using Hybrid Analog-Digital Circuit Taherinejad, N.; Abrishamifar, A.; Circuit Theory and Design, ECCTD European Conference on Digital Object Identifier: /ECCTD Publication Year: 2009, Page(s): Adviser : 易昶霈 Student : 杜彥諴

Outline 1.Introduction 2.Proposed Hybrid Analog-Digital Circuit 3.Simulation 4.Discussion 5.Conclusion

Introduction  (CellPhone, NB, MP3)Mobile system's process  Hybrid analog-digital circuit design  Analysis general structure of a full adder and delay propagation  Critical path delay

Introduction  Analysis General Structure of a Full Adder and Delay Propagation 假設一個邏輯閘的延遲時間為 t ， FA 最大的延遲 時間為 carry out(3t)

Introduction  Critical Path Delay 以 ADDER 來說不管是常見 RCA 還是 CLA 在 carry 通常以 delay 最大的

Proposed Hybrid Analog-Digital Circuit  Carry Propagation  Summation  Three regions

Proposed Hybrid Analog-Digital Circuit  Carry Propagation A new circuit for carry propagation Table-1

Proposed Hybrid Analog-Digital Circuit  Carry Propagation A new circuit for carry propagation 無論是一個 FA 或是 n 個 bit adder ， carry 都是最慢 的一個因素 這裡本文提出了一個用混合設計的概念電路 將原本的 3t 電路改成 2t 電路

Proposed Hybrid Analog-Digital Circuit  Carry Propagation A new circuit for carry propagation

Proposed Hybrid Analog-Digital Circuit  Carry Propagation A new circuit for carry propagation

Proposed Hybrid Analog-Digital Circuit  Carry Propagation Table-1

Proposed Hybrid Analog-Digital Circuit  Summation

Proposed Hybrid Analog-Digital Circuit  Summation final circuit

Proposed Hybrid Analog-Digital Circuit  Three regions Logical low(0~0.6 V) Meaningless(0.6~1.2 V) Logical high(1.2~1.8 V)

Simulation  Table-2 Minimum mos specification

Simulation  Table-3 Other special mos specification

Discussion  delay

Discussion  power

Discussion  Table-4

Conclusion  在不計算 Paper 中 Cout 錯誤的狀況下，此電 路只使用 6(Sout)+10(Cout) 。與文中所示 之一般 Adder(24) 相比，減少了 3 成的 mos 數量  減少了 Carry 的延遲時間，速度由 3t 改善至 2t ，減少了 3 成的時間