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 Why Digital RF?  Digital processors are typically implemented in the latest CMOS process → Take advantages scaling. (e.g. density,performance)  Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind digital transistor models by several quarters. → time-to-market and multiple-chip  Traditional RF circuits do not benefit from scaling as digital circuits do.(e.g. due to extensive use of inductors, the ever-lowering supply voltage) Ref. : [2] Basic Concepts – Digital RF 2

 The frequency of oscillators in RF transceivers must be defined with very high absolute accuracy.  In most cases the frequency must also be varied in small, precise steps, thus it must be adjustable. [3] e.g. for GSM-1800 System mobile radio networks -374 frequency channels -Bandwidth of 200 KHz are available each channel. -The uplink uses the frequencies 1710 ~ 1785 MHz -The downlink uses the frequencies 1805~1880 MHz. In other words, to change the receive or channel, the LO frequency may be required to vary by only 200 kHz. [4] Basic Concepts – Frequency Synthesizer 3

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 PLL (Phase Locked Loop) A feedback system to lock the output frequency on the input one. Phase Detector: error amplifier. Low-Pass Filter: allows the dc value to control the VCO frequency. VCO : Voltage Controlled Oscillator Basic Concepts – PLL & VCO [3] 5

 VCO can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios.  To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency with respect to the PA.  This paper proposes a reconfigurable fractional divider capable of covering the WiFi 2.4~2.5GHz and 5~5.8GHz, and WiMAX 2.3~2.7GHz and 3.3~3.8GHz standards with a single VCO with 20% tuning range.  The divider is all-digital, hence scaling-friendly, …  The versatility is afforded by the reconfigurable fractional divider. This Work – Proposal 6

 4 quadrature input phases P 1 ~P 4 (Phase Rotator): A high-speed mux with stringent timing constraints.  Each phase is divided by 5 using a Johnson counter (JC)  Output of JC is sampled by the corresponding phase using a set-reset latch.  Signals A-D are combined using an OR gate.  The divider can be changed by simply varying the integer division of the counters, e.g. to 3 for ÷0.75 or 7 for ÷1.75. This Work - Architecture of Reconfigurable Fractional Frequency Divider ÷1.25 [1] Spectral purity of the output is determined by the matching between the 4 path delays. 7

This Work - Digitally Controlled Delay Line  Digitally tunable delays independently adjusting rising and falling edge are used to correct mismatch between the paths.  DCDL: ~1ps resolution : inverters partially starved by enabling or disabling parallel transistors.  5b 1 st -order ΔΣ modulator, driving an RC filter (pole~4MHz) : Tune the MOS cap load of an inverter and obtain ~60fs delay resolution.  The tunable delay cells operate at the Johnson counters output frequency. [1] 8

Implementation (1) - Standalone Fractional Divider [1]  Implemented standalone in 32nm CMOS.  The divider generates LO signals  Quadrature inputs generated by a divider-by-2.  A single VCO with 20% tuning range (7.8 to 9.5GHz). Consuming from 1.05V Spurs Suppression WiFi/WiMax bands: 5.9 mA<-60 dBc2.5 GHz 6.8 mA<-57 dBc3.5 GHz 8.3 mA<-48 dBc5.5 GHz 9

This Work - Digitally Controlled Delay Line  If an interferer is detected, both f vco and the divider ratio are changed by inverse factors such that the synthesized RF channel (f rf ) remains unchanged: f rf = f vco,1 / r 1 = f vco,2 / r 2  Interference can be detected from the VCO control voltage and is ideally suited to digital PLL implementations, where the control voltage is readily available for DSP processing. 10

This Work - Block Diagram of the LO Generation [1]  Two identical fractional dividers (frac-div1 and fracdiv2) are used  Digital Duty-Cycle Corrector (DCC) : correct the non-50% duty cycle output.  Digital DLL generates I&Q LO phases for the TX/RX mixers.  MUXes allow for fracdiv1 and fracdiv2 to be placed in series or for fracdiv2 to be bypassed  To save power fracdiv2 is only enabled when an interferer is detected. 11

Implementation (2) – On the fly Interference Management [1] Interferer : 100kHz offset from f vco =8750MHz 9375MHz & ÷3.75Mode 8750MHz & ÷3.5Mode No Interferer -29dB-19dB-29dBEVM 0.4mm2 -Die Area 30 mA22 mA-consuming from Vdd=1.05V The all-digital 32nm LOG uses digital calibration instead of spur-filtering inductors and lends itself to CMOS scaling. 12

Implementation (3) – Die Micrograph 13

[1] K. Chandrashekar et. al., "A 32nm CMOS ALL-Digital Reconfigurable Fractional Frequency Divider for LO Generation in Multistandard SoC Radios With On-the-Fly Interference Management", ISSCC Dig. Tech. Papers, pp , Feb [2] K. Chandrashekar et. al., " A 20dBm 2.4GHz Digital Outphasing Transmitter for WLAN Application in 32nm CMOS ", ISSCC Dig. Tech. Papers, pp , Feb [3] Razavi, Behzad. RF microelectronics. Upper Saddle River, NJ: Prentice Hall, Print. [4] gsmserver.com, “GSM Characteristics” available on: References 14

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