Hardware implement 涂正中. 2010:Convolutional Networks and Applications in Vision （ Overview ） Chip: first :1991-1992, Bell Labs’ ANNA chip. ConvNet chip.

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Presentation transcript:

Hardware implement 涂正中

2010:Convolutional Networks and Applications in Vision （ Overview ） Chip: first : , Bell Labs’ ANNA chip. ConvNet chip from Canon team 2009:CAVIAR ; Addressed-Event Representation (AER) convolvers FPGA: Vip:An fpga-based processor for image processing and neural networks(1996) CNP:(2009)

ANNA chip(analog neural network arithmetic and logic unit)(1992) in a 0.9 um CMOS technology contains transistors on a 4.5 x 7 mm2 die Although the chip uses analog computing internally, all input/output is digital. (mixed analog/digital) combines the advantages of high synaptic density, high speed, low power of analog, and easy interfacing to a digital system such as a digital signal processor (DSP).

ANNA chip Architechture

ANNA chip application For Handwritten digits implement Error rate :about 5% maximum of 10 9 connections per second (10 GC/s), actually much lower

CAVIAR (Convolution AER Vision Architecture for Real-Time) (Addressed-Event Representation,AER) 卷积器不需要乘法器计算卷积 4 mixed-signal AER chips 论文太长太难（主要用 AER ，也不好找资料）

CAVIAR

CNP(ConvNet Processor)(2009) A single FPGA with an external memory module

CNP Architechture

2D Conv Parallel pipelined 逐行扫描

APP to face detection (Training Architecture)

Network Architecture Built and trained on a computer using the Lush language,and compiled to the CNP using the automatic ConvNet compiler. Trained on images, for testing. Roughly 3% equal error rate after 5 epochs’ training.

Speed 4 billion connections per second on average Time spent on pre/post processing and data fetcing Process 512 X 384 greyscale image(LeNet) frames per second

2010/Hardware Accelerated Convolutional Neural Networks

2010

2013_ The Multi 2D Systolic Design

Architecture

Reference ISCAS2010_Convolutional_Networks_and_Applications_in_Vision IEEE1992_Application of the ANNA Neural Network IEEE2009_CAVIAR_Canon corparationCAVIAR 2009_CNP_AN_FPGA_BASED_PROCESSOR_FOR_CONVOLUTIONAL_NET WORKS ISCAS2010_Hardware_Accelerated_Convolutional_Neural ICECS2013The_Multi_2D_Systolic_Design_and_Implementation_of_Con volutional_Neural_Networks