Platform ASICs Reliability Bob Madge Miguel Vilchis LSI Logic, Milpitas, CA Vish Bhide

#141 MAPLD 2005Bob Madge2 Three Aspects of Reliability  Infant Mortality Failures (Latent Defects and active defects that are not screenable with Testing)  Environmental induced Failures (SER etc..)  Intrinsic Failures (Stress migration, electromigration, Wear-out, performance degradation)

#141 MAPLD 2005Bob Madge3 Methods for Optimizing Reliability  Design For Reliability Design for Defect Tolerance Design for SER tolerance Design for Stress Migration Tolerance Redundancy  Process Improvements Defect Density Reduction Excursion Control  Test Improvements Resistive Defect Fault Coverage Un-modeled fault coverage Statistical Testing

#141 MAPLD 2005Bob Madge4 Platform ASIC – Infrastructure for Reliability Embedded Test and Repair Optimized Regular Logic Pre-Verified IP Process Monitor and Die Traceability Optimized Memory Configurable I/O

#141 MAPLD 2005Bob Madge5 Platform ASIC Design For Reliability  Allowable antenna ratios have a 3x margin  Additional protection against plasma induced damage  Protection against wearout mechanisms Stress Migration Electro Migration Hot Carrier Injection Time Dependent Dielectric Breakdown Vt stability  The rules are considered conservative within the industry  The rules are tested for fabrication capability, yield and reliability during qualification  The libraries and layout tools strictly follow the design rules Cells with intentional design rule violations require qualification  Tools such as relmil, BERT are available to the designers

#141 MAPLD 2005Bob Madge6 Statistical Reliability Control

#141 MAPLD 2005Bob Madge7 Continuous feedback and improvement  During Development: Library elements are redesigned during the development cycle if design rules change Process/Tool changes are made if the libraries cannot change  During production: The customer issues are continuously fed back Process changes are made if applicable Cell changes are made if necessary Current customers are protected by the MRB/TRB systems Redesigns incorporate the changes if necessary Future customers only receive the revised version Identification of issues by one customer benefits all others

#141 MAPLD 2005Bob Madge8 Single Event Effects Mitigation  LSI Logic platform ASICs using 0.18 um CMOS commercial process are designed using best practices for SEE mitigation optimization of n-well spacing and profile buried layer for latchup mitigation  The mitigation strategies lead to SEL immunity to atmospheric neutron fluence of 5E10 n/cm 2 and SEU cross section of 4E-14 cm 2 /bit. This performance is superior to a typical commercial grade product.  On chip error correction codes (ECC) for memory devices are available word interleaving for multi bit error mitigation

#141 MAPLD 2005Bob Madge9 Radiation Performance  Unlike commercial grade products, Platform ASICs using a 0.18 um CMOS modified process have been characterized for Total Ionizing Dose (TID), functional up to the maximum dose level of 300 krad-Si no noticeable degradation up to a total dose of 90 krad-Si.  Unlike commercial grade products, Platform ASICs using a 0.18 um CMOS modified process have been characterized for heavy ion Single Event Effects (SEE) At LET of 75 MeV cm 2 /mg logic and SRAM blocks are immune to single event latchup (SEL) Single Event Upset saturation cross sections are 1E-06 cm 2 /bit and 7E-07 cm 2 /flip-flop  Additionally, Platform ASICs using a um CMOS modified process have been characterized for heavy ion Single Event Effects (SEE) At LET of 108 MeV cm 2 /mg logic and SRAM blocks are immune to single event latchup (SEL) Single Event Upset cross sections data is under evaluation

#141 MAPLD 2005Bob Madge10 Efficient Netlist Implementation  Early and Intrinsic Failure rates and Soft Error Rates are proportional to the number of used gates and SRAM  The platform ASICs implement the the RTL with minimum overhead of logic gates and require no configuration SRAM  Efficient Implementation through mask configuration leads to lower product failure rate than a product that requires more gates to implement the same functionality

#141 MAPLD 2005Bob Madge11 Maverick Silicon Screening Procedures  Lot Level Lot Yield limits,Lot Acceptance testing >>>Minimum Quality  Wafer Level Wafer Yield limits, Statistical Bin Limits Maverick Lot Control >>>>Medium Quality  Die Level Iddq, VDD and Fmax Outlier Screening Dynamic and Enhanced Voltage Stress testing Adaptive Thresholds and limits Neighborhood Association or location Exclusion >>>>Maximum quality

#141 MAPLD 2005Bob Madge12 Targeted Defect Coverage  Reported Fault Coverage Tool reported Scan (target 99%), Iddq, Memory, Delay fault coverage.  Weighted Fault Coverage (Test Coverage) Reported Fault Coverage weighted by Area of the chip.  Defect Coverage Is a factor of : Weighted Fault Coverage, Fab. Defectivity Frequency, Gate Count and Outlier Screening Efficiency. Drives EFR and DPM Target 99.9%

#141 MAPLD 2005Bob Madge13 LSI Logic Statistical Post-Processing™ Test Flow Wafer Test with full data collection and inkless wafermaps Post-processor #1 : Delta IDDq / MinVDD Post-processor #3 : Independent Component Analysis (ICA) Post-processor #2 : Neighborhood Residual (NNR) and Exclusion (NAE) Inkless Assembly Burn-in (special bins only) Final package test SHIP Modify Inkless Maps (upgrade or downgrade into special bins) (Final Test Post- Processing) Data Wafers Post-Processor #4: Temperature Ratios

#141 MAPLD 2005Bob Madge14 SPP: Value Application: Burn-in elimination or reduction Burn-in candidates Rejection candidates

#141 MAPLD 2005Bob Madge15 Speed Current Count Signal Overlap in Current Vs Speed

#141 MAPLD 2005Bob Madge16 Statistical Post-Processing™ (SPP) used to Screen Test Outliers.  SPP Concept # 1: Delta Iddq/MinV DD The delta between the Iddq or MinV DD of discrete tests or vectors within a device can be used to distinguish between defective die and defect-free die.  SPP Concept # 2: Nearest Neighbor Residual (NNR) If Iddq/MinV DD for a given die location on a wafer is significantly higher than it’s neighbors, that die can be considered defective.  SPP Concept #3 : Independent Component Analysis (ICA) Identification and elimination of independent sources of parametric variation for defect identification.  SPP Concept #4 : Temperature Ratio Testing (US Patent Issue No. 6,532,431) Ratio of test parameters (Iddq, MinVDD, Fmax) at two different temperatures can be used to distinguish between defective and defect free die.

#141 MAPLD 2005Bob Madge17 SPP to Screen MinV DD Outliers : “Nearest Neighbor Analysis (NNR)” NNR Outliers

#141 MAPLD 2005Bob Madge18 Intrinsic Estimate Residual Count Defect Signal Resolution after Post-Processing SPP Limit

#141 MAPLD 2005Bob Madge19 Resistive Defect Outlier Screening Resistive unfilled W Via

#141 MAPLD 2005Bob Madge20 The two RMA parts are Feed- Forward MinVDD Outliers SPP Screening Temperature Dependant Defects

#141 MAPLD 2005Bob Madge21 Downgrades at increasing “stringency” Good Die in Bad Neighborhoods – Latent Defect Post-Processing In production on G12

#141 MAPLD 2005Bob Madge22 Location Based Downgrades Downgrade “good die” in “at-risk” locations like the edge

#141 MAPLD 2005Bob Madge23 SPP: Application: New Technology Defectivity Control Defect Density Time Quality Time Defect Density Time SPP Stringency Time Quality Time Quality Ramp Guarantee Pre-emptive Variable Threshold control function

#141 MAPLD 2005Bob Madge24 SPP: Application: Process Fluctuations and Maverick Lot Control Quality Time Feed Forward SPP Stringency Time Defect Density Time Quality Time Pre-emptive Variable Threshold control function Feed-forward Variable Threshold control function Defect Density Time Quality Ramp Guarantee

#141 MAPLD 2005Bob Madge25 Quality improvement due to Statistical Post-Processing™ Overall EFR without SPP Overall EFR with SPP EFR/DPMDD Months

#141 MAPLD 2005Bob Madge26 Reliability Improvement : Burn-in Results for SPP Outliers

#141 MAPLD 2005Bob Madge27  Overall data show at least 56% effectiveness.  The EFR estimate for Bin1 population is data limited and likely to be at least 50% lower  Therefore the overall effectiveness number is likely to be much higher.