Optics in Internet Routers Mark Horowitz, Nick McKeown, Olav Solgaard, David Miller Stanford University

2 0, Fiber Capacity (Gbit/s) TDMDWDM Packet processing PowerLink Speed 2x / 18 months2x / 7 months Source: SPEC95Int & David Miller, Stanford Why We Need Faster Routers To prevent routers from becoming the bottleneck

3 POP with smaller routersPOP with large routers Interfaces: Price >$100k, Power > 400W It is common for 50-60% of interfaces to be for interconnection within the POP Industry trend is towards large, single router per POP Fast (Large) Routers Big POPs need big routers

4 A router is a packet-switch, and therefore requires A switch fabric Per-packet address lookup Large buffers for times of congestion Address lookup and buffering are infeasible using optics presently A typical 10 Gb/s router linecard has 30 Mgates and 2.5 Gbits of memory Research Problem How to optimize the architecture of a router that uses an optical switch fabric? All optical IP routers are infeasible today

5 100 Tb/s Optical Router Collaboration 4 Stanford professors (M. Horowitz, N. McKeown, D. Miller and O. Solgaard), and their groups Objective To determine the best way to incorporate optics into routers Push technology hard to expose new issues Photonics, Electronics, System design Motivating example: The design of a 100 Tb/s Internet router Challenging but not impossible (~100x current systems) It identifies some interesting research problems

6 Arbitration 160Gb/s 40Gb/s Optical Switch Line termination IP packet processing Packet buffering Line termination IP packet processing Packet buffering Gb/s Gb/s Electronic Linecard #1 Electronic Linecard #625 Request Grant (100Tb/s = 625 * 160Gb/s) 100 Tb/s Router

7 Research Problems Linecard Memory bottleneck: Address lookup and packet buffering Architecture Arbitration: Computation complexity Switch Fabric Optics: Fabric scalability and speed Electronics: Switch control and link electronics Packaging: Three surface problem

8 160Gb/s Linecard: Packet Buffering Problem Packet buffer needs density of DRAM (40 Gbits) and speed of SRAM (2ns per packet) Solution Hybrid solution uses on-chip SRAM and off-chip DRAM Identified optimal algorithms that minimize size of SRAM (12 Mbits) Precisely emulates behavior of 40 Gbit, 2ns SRAM DRAM 160 Gb/s Queue Manager [klamath.stanford.edu/~sundaes/Papers/ieeehpsr2001.pdf] SRAM

9 Architecture: The Arbitration Problem A packet switch fabric is reconfigured for every packet transfer At 160Gb/s, a new IP packet can arrive every 2ns The configuration is picked to maximize throughput and not waste capacity Known algorithms are too slow Our solution is to eliminate the arbitration

10 Two-Stage Switch External Outputs Internal Inputs 1 N External Inputs Spanning Set of Permutations 1 N 1 N Recently shown to maximize throughput [C.S.Chang et al.:

11 Problem: Unbounded Mis-sequencing External Outputs Internal Inputs 1 N External Inputs Spanning Set of Permutations 1 N 1 N We have developed an algorithm to Keep packets ordered and Guarantee a delay bound within the optimum [Infocom’02: klamath.stanford.edu/~keslassy/download/infocom02_two_stage.pdf]

Phase 2 Phase 1 Idea: use a single-stage twice An Optical Two-stage Switch Lookup Buffer Lookup Buffer Lookup Buffer Linecards

13 Cascaded Wavelength Switches mn x mn switching fabric 2n building blocks Supports spanning set of permutations 1 Input m Input 2 Input 1 2 Input m Input 2 Input 1 n Input m Input 2 Input 1 1 Output m Output 2 Output 1 2 Output m Output 2 Output 1 n Output m Output 2 Output 1

14 Building Block: Wavelength Switch m -Input and n -Output Switching by wavelength selection of tunable lasers Optical amplifier (EDFA) can be included to reduce loss Input 1 Input 2 Input m 1, 2, …, n Output 1 Output 2 Output n 1 2 n Power Combiner Wavelength Demultiplexer

15 Wavelength Switch:Receiver Side n -Input and m -Output Tunable optical filters are key components Output 1 Output 2 Output m Input 1 Input 2 Input n 1 2 n Power Divider Wavelength Multiplexer Tunable Filters

16 Arrays of Optoelectronic Transceivers CMOS Optical Receiver A 1.6Gb/s, 3mW Integrating CMOS Optical Receiver with AlGaAs Photo-Detectors Standard CMOS Electronics with flip-chip bonded optical devices Removes the trans-impedance amplifier to reduce power and improve bit-rate. Enables dense arrays of receivers and transmitters on chip

17 A Novel Double Sampling, Integrating Receiver: No Linear Amplification, No Transimpedance Amplifier Integrates the optically generated current into the parasitic input capacitor Samples the voltage of the input node at two consecutive bit times Compares these two values with the following clocked Sense Amp/StrongArm Latches Adjusts the DC input voltage and subtracts the DC current from the input node with a feedback controlled DC current Source Consumes very Low Power, small Area while Bandwidth and Sensitivity are Comparable with TIA Receivers Receiver Design

18 Architecture Study performance of two-stage switch with Internet traffic Study feasibility of algorithms that prevent mis-sequencing Linecard Explore parallel address lookup and packet buffer schemes Design, and possibly prototype, a 160Gb/s router linecard Future Architecture/Linecard Work

19 Future Optics Work Waveguide Switch Use commercial devices such as Array Waveguide Grating Tunable Wavelength Switch Lossless Compact Tunable Optical Filter Fast (< 100 ns) More than 100 addressable channels MEMS Gires-Tournois interferometers

20 Switch Control Feedback using link amplitude information Plan on building a circuit/chip that can control some part of the optical switch. Photonic links Continue working on high-speed, low-power, CMOS VLSI photonics receivers, transmitters and clock recovery. Devise circuits that can interface to a high-speed optical switch. Tunable MSM photodetector. Future Electronics Work

21 Proposed work Wavelength splitter without coupling losses Extension of a photonic crystal wavelength splitters Packaging for photonic chips Future Packaging Work Through which surface do you get the light? Heat Power

22 Conclusion 100Tb/s is a good driver for wireline thrust Also help drive Robust and Chip in a Day thrusts Collaboration of people working on router architecture, electronics, optics and packaging. Interaction really matter Two stage switch helps line-card, optical switch Already have results in 4 of 5 areas Just starting the packaging effort