CMP 301A Computer Architecture 1 Lecture 3

Outline zQuick summary zMultilevel cache zVirtual memory y Motivation and Terminology y Page Table y Translation Lookaside Buffer (TLB)

Summary: Sources of Cache Misses zCompulsory (cold start, first reference): first access to a block  Misses that would occur even with infinite cache y“Cold” fact of life: not a whole lot you can do about it 1.Increase block size zConflict (collision): yMultiple memory locations mapped to the same cache location 1.Increase cache size 2.Increase associativity 3.Reduce block size “for the same size cache” zCapacity: yCache cannot contain all blocks accessed by the program 1.Increase cache size

4 Summary: Effect of Cache Parameters on Performance Larger cache size + reduces capacity and conflict misses - hit time will increase Higher associativity + reduces conflict misses - may increase hit time Larger block size + reduces compulsory misses and reload - increases conflict misses and miss penalty

5 Summary: The Cache Design Space zSeveral interacting dimensions ycache size yblock size yassociativity yreplacement policy ywrite-through vs. write-back zThe optimal choice is a compromise ydepends on access characteristics ydepends on technology / cost zSimplicity often wins Associativity Cache Size Block Size Bad Good LessMore Factor AFactor B

6 Multilevel cache zUse smaller L1 if there is also L2 zTrade increased L1 miss rate for reduced L1 hit time and reduced L1 miss penalty zReduces average access time CPU L1 L2 DRAM

Multilevel cache – Example You are building a system around a processor running at 2.0 GHz. The processor has a CPI of 0.5 excluding memory stalls. 30% of the instructions are loads and stores. The memory system is composed of separate L1 instruction and data caches that imposes no penalty on hits. The L1-cache has a miss rate of 3% for both instructions and data and has 32-byte blocks. The unified L2 cache has 64-byte blocks and an access time of 25ns. It is connected to the L1 cache by a 256-bit data bus that runs at 500MHz and can transfer one 256-bit bus word per bus cycle. Of all memory references sent to the L2 cache, 90% are satisfied without going to the main memory. The main memory has an access latency of 200ns, after which any number of bus words may be transferred at the rate of one per cycle on the 128-bit-wide 250MHz main memory bus. What is the overall CPI?

Virtual Memory: Motivations zRemove the programming burdens of a small limited amount of main memory yProgrammers moved the data back and forth from the secondary store by overlaying it repeatedly on the primary store  Tricky programming zAllow efficient and safe sharing of memory among multiple programs yEasier to compile each programs to its own address space yVirtual memory then map these virtual addresses to physical addresses yAllow for reallocation “not even necessarily to be contiguous”

Basic Terminology zMain memory acts as a cache for secondary storage “magnetic disk” zPage : Virtual memory block “similar to cache block” zPage Fault: Virtual memory miss “similar to cache miss” zVirtual address: Address generated by the processor zPhysical address: Actual address to access the main memory zAddress Translation: Mapping virtual address to physical one

Virtual Memory Design Decisions zPage fault is very costly (Millions of clock cycles) 1.Use a large page size to amortize from the large access time (4-64 kB) 2.Use fully associative placement to reduce page fault rate 3.Use clever placement algorithms (even software techniques) 4.Use Write back not write through as writing is costly

Virtual to physical Address Mapping