Transition Radiation Detector Gas Slow Control System AMS-02 A. Bartoloni a, B.Borgia a, S. Gentile a G. Amelino Camelia a, S. Baccaro b, C. Bosio a, C. Gargiulo a, G. La Neve c, A. Paolozzi c, P. Rapagnani a,E. Valente a a- INFN Sezione di Roma b- ENEA – CR Casaccia c- Dip. Ing. Aerospaziale, Università “La Sapienza” Roma

Gas System Slow Control 120VDC Box-CBox-S PDB USCM JMDC Monitoring and Control Computer CAN-BUS MANIFOLD TRD GAS SYSTEM UGM modules 28VDC Ctrl&Mon Signals 1553 SRDL (NASA Avionics) UGE-crate DC-DC converters UGBC board UGM boards UGBS board TRD Power Supply HV Safety Signal to U Crate UGpd-box Filter Ctrl Gas Mixture

UGE crate prototypes 11 Boards 6U height (AMS VME type) 2 slots USCM dedicated 9 slots for control boards All control boards use FPGA to interface the USCM bus and to pilot the device drivers 2 boards to control the BOX-S (UGBS) 13 solenoid valves 4 press. & temp. sensors 2 boards to control the BOX-C (UGBC) 2 circulation pumps 4 solenoid valves 3 flipper valves 3 press. & temp. sensors 1 CO 2 analyzer (RS232) 1 MCA (RS232) 1 monitor tubes 1 board for BOX-C monitor tubes power supply(UHVG) 4 boards for Manifold control 4 to control the 164 flipper valves located in the manifolds (UGFV-AC., UGFV-BD) logics for 82 pressure sensor signals multiplexing will be inserted in the UGFV boards hot boards cold boards UGE CRATE Backplane board UGBS UGBC’ USCM USCM’ UGBC UGFV-BD + Mux-PB UGFV-AC + Mux-PA UGBS’ UHVG UGFV-AC’ + Mux-PAUGFV-BD’ + Mux-PB

Project Status Prototypes developments - boards electrical schematic ready - the whole functionalities addressed - basic control circuits simulated (PSPICE) - complex functionality components taken from the AMS preferred part list - simpler components (MOSFET) selected using derating criteria - firm selected for PCBs design and production (ProSer S.r.l.) - UGBC board ready (yesterday !!) - UGBS board PCB developed (expected ready next week) - UGFV & UGM module PCBs in development (expected ready in August) - backplane schematics in development (released after )

UGBC interface to BOX-C Tasks: switch on/off and regulate speed of circulation pumps open the valves test the status of the valves monitor pressure and temperature sensor emergency open of safety valves without USCM intervention manage emergency in case of massive gas leak Redundancy: hot & cold (hot & hot will be evaluated against power budget) no duplication of control circuits on the same board

UGBC

Front panels

All boards use the same USCM I/O BUS interface logic: LVDS Receiver LVDS Driver A54SX32A FPGA (PQFP 208) VHDL is used to describe FPGA logic The ACTEL development environment is used Libero Software Silicon Sculptor Silicon Explorer LVDS REC. LVDS DRIV. Data(15:0) Address(7:0), RW, ST, AKN, ….. A54SX32A JTAG Board I/O

USCM USCM’ UHVG UGE backplane using Le Croy bus UHVG’ UGBSUGBS’UGBCUGBC’ UGFV AC UGFV AC’ UGFV BD UGFV BD’

USCM USCM’ UHVG DIO16+ (ADD0+) DIO16- (ADD0-) DIO16+ (ADD0+) DIO16- (ADD0-) pCLKA nCLKA DIO17+ (ADD1+) DIO17- (ADD1-) DIO17+ (ADD1+) DIO17- (ADD1-) pCLKB nCLKB 100Ώ Backplane UHVG address backplane UHVG’

USCM DIO0+ (DATA0+) DIO0- (DATA0-) DIO0+ (DATA0+) DIO0- (DATA0-) pDataA nDataA DIO1+ (DATA1+) DIO1- (DATA1-) DIO1+ (DATA1+) DIO1- (DATA1-) pDataB nDataB 100Ώ Backplane 100Ώ UHVG data backplane USCM’ UHVG UHVG’

USCM USCM’ UGxx UST+, DIO2+ (RESET+) STR+, RESET+ STR-, RESET- 100Ώ Backplane UST-, DIO2- (RESET-) BGO+ (UST+), DIO3+ (RESET+) BGO- (UST-), DIO3- (RESET-) UGxx’ UGxx controls backplane STR+, RESET+ STR-, RESET- UST+, DIO2+ (RESET+) UST-, DIO2- (RESET-) BGO+ (UST+), DIO3+ (RESET+) BGO- (UST-), DIO3- (RESET-)

USCM ACK+ 100Ώ UGxx ACK+ ACK- Backplane ACK+ ACK- BRI+ (ACK+) BRI- (ACK-) UGxx controls (ACK) backplane USCM’ UGxx’ ACK+ ACK- BRI+ (ACK+) BRI- (ACK-)

USCM USCM’ UGxx DIO+[18:20] (ADD+[2:4]) ADD+(0:1),AddParityBit ADD-(0:1),AddParityBit 100Ώ Backplane DIO-[18:20] (ADD-[2:4]) DIO+[21:23] (ADD+[5:7]) DIO-[21:23] (ADD-[5:7]) UGxx’ ADD+(0:1), AddParityBit ADD-(0:1), AddParityBit UGxx address backplane DIO+[18:20] (ADD+[2:4]) DIO-[18:20] (ADD-[2:4]) DIO+[21:23] (ADD+[5:7]) DIO-[21:23] (ADD-[5:7])

USCM DIO+[4:9] (DATA+[4:9]) 100Ώ UGxx DATA+(0:4),DataParityBit DATA-(0:4),DataParityBit 100Ώ Backplane DATA+(0:4),DataParityBit DATA-(0:4),DataParityBit DIO-[4:9] (DATA-[4:9]) DIO+[10:15] (DATA+[10:15]) DIO-[10:15] (DATA-[10:15]) UGxx data backplane USCM’ UGxx’ DIO+[4:9] (DATA+[4:9]) DIO-[4:9] (DATA-[4:9]) DIO+[10:15] (DATA+[10:15]) DIO-[10:15] (DATA-[10:15])

UGxx I/O protocol UST ACK ADD(1:0) DATA(4:0) DataParityBit USCM : Put UGxx Address, Command, Parity bits on bus USCM : flags Ugxx setting UST UGxx (ALL) : Latch Data on the bus UGxx (ALL) : Decode Address Add. UGxx : Flag USCM setting ACK USCM : Release Bus USCM : Reset UST Add Ugxx : Reset ACK AddParityBit Command Write Cycle Command UGxx Address Command UGxx Address Command Read “Back” Cycle USCM : Put UGxx Address, AddParity USCM : flags Ugxx setting UST UGxx (ALL) : Latch Add on the bus UGxx (ALL) : Decode Address Add. UGxx : Put Rx Cmd + Parity on the Bus Add. UGxx : Flag USCM setting ACK USCM : Latch DataBus USCM : Reset UST Add Ugxx : Reset ACK The addressed Ugxx will replay to this read request only if all is OK during the previous write cycle (parity checking, cmd decoding). no replay means also that command it is not executed by the UGxx Depending on the command 0 to 3 Write or Read cycle Could happen. In case of writes a Read cycle at the end will flag the USCM that all is OK

UGBC commands -- Data Function Reserved Write MV100 Enable Register (1W) Read MV100 Enable Register (1R) Write Open Time Register (3W) Read Open Time Register (3R) Write Pump Enable&Speed Register (1W) Read Pump Enable&Speed Register (1R) Write MCA select Register (1W) Read MCA select Register (1R) Read Current Status Register (3R) Read Event Status Register (3R) Open Valve V6a (0) Open Valve V6b (0) Open Valve V18a (0) Open Valve V18b (0) Open Valve V6a and V18a (0) -- Data Function Open Valve V6b and V18b (0) Open Valve V8a (0) Close Valve V8a (0) Open Valve V8b (0) Close Valve V8b (0) Activate HV Safety Signal (1W) Read P4 value (3R) Read T4 value (3R) Read P5 value (3R) Read T5 value (3R) Read P6 value (3R) Read T6 value (3R) Read CP1 current (3R) Read CP2 current (3R) Write RS232 register (1W) Read RS232 register (1R)

UGBS commands -- Data Function Reserved Write MV100 Enable Register (3W) Read MV100 Enable Register (3R) Write Open Time Register (3W) Read Open Time Register (3R) Read El. Current Status Register (3R) Read El. Event Status Register (3R) Read Mech. Event Status Register (3R) Read Mech. Event Status Register (3R) Open Valve V1a (0) Open Valve V’1a (0) Open Valve V1b (0) Open Valve V’1b (0) Open Valve V2a (0) Open Valve V2b (0) Open Valve V3a (0) -- Data Function Open Valve V3b (0) Open Valve V4 (0) Open Valve V’4 (0) Open Valve V5 (0) Open Valve V20a (0) Open Valve V20b (0) Open Valve V20a and V20b (0) Read P1A value (3R) Read T1A value (3R) Read P1B value (3R) Read T1B value (3R) Read P2A value (3R) Read T2A value (3R) Read P2B value (3R) Read T2B register (3R) Reserved

UGFV commands -- Data Function Reserved Write PS Enable Register (1W) Read PS Enable Register (1R) Open On Module 1 (3W) Close On Module 1 (3W) Open On Module 2 (3W) Close On Module 2 (3W) Open On Module 3 (3W) Close On Module 3 (3W) Open On Module 4 (3W) Close On Module 4 (3W) Open On Module 5 (3W) Close On Module 5 (3W) Open On Module 6 (3W) Close On Module 6 (3W) Open On Module 7 (3W) -- Data Function Close On Module 7 (3W) Open On Module 8 (3W) Close On Module 8 (3W) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

“Le Croy Bus” protocol for UGE RECEIVE CYCLE -- S(1) = 1 -- S(2) Parity bit (odd) -- S(3) Power Down Bit -- S(4) Broadcast Bit -- S(5:12) Select Code -- S(13) RD/WR bit -- S(14:16) Section Address -- S(17:32) Data to be written TRANSMIT CYCLE -- S(33) = 0 -- S(34) echo of S(2) -- S(35) echo of S(3) -- S(36) echo of S(4) -- S(37:44) echo of S(5:12) -- S(45) echo of S(13) -- S(39:41) echo of S(14:16) -- S(42:64) Data to be read UGBC Section Address 000 MV100, MCA, Pump Register 001 Open Time Register 010 Curr. or Event Status Reg. 011 RS232 Status Register 100 Reserved 101 Valve Control 110 HV safety Signal Control 111 P&T Sensors UGBS Section Address 000 MV100 Register 001 Open Time Register 010 Curr. or Event Status Reg. 011 Reserved 100 Reserved 101 Valve Control 110 Reserved 111 P&T Sensors UGFV Section Address 000 PS Control Register 001 Module 1&2 010 Module 3&4 011 Module 5&6 100 Module 7&8 101 Reserved 110 Reserved 111 Reserved

Pump control circuit is based on three switches Pump energizing requires two different steps 1)Pump connection to the power supply is done using SW-1 2)Pump is energized using SW-2 (full speed) or SW-3 (half speed) Energized and Speed status of the valve are stored in the FPGA through the use of comparators monitoring the voltage applied to the pump and of ADC monitoring the surged current GND +24 From FPGA SW-1 SW-2 R SW-3 Part List: N-Mosfet SUB85N10 (ID = 85A, VDS = 100V) P-Mosfet SUB65N06 (ID = -65A, VDS = -60V) N-Mosfet Si4840DY (ID = 10A, VDS = 40V) Comparator LM bits ADC AD7476

MV100 valve control circuit is based on two switches Valve energizing requires two different steps 1)Valve connection to the 24 V power supply is done using SW-1 2)Valve is closed using SW-2 Energized status of the valve is stored in the FPGA through the use of a comparator (LM239) monitoring the voltage applied to the valve Mechanical status of the valve is stored in the FPGA using the valve position switch signals (after debouncing) Open time (miminum of 50 ms up to 30 seconds) is programmable by USCM To implement the switch Vishay P-Mosfet and N-mosfet are used : SUB85N10 (ID = 85A, VDS = 100V) SUB65P06 (ID = 65A, VDS = 60V) Si4840DY (ID = 10A, VDS = 40V) GND +24 LM239 MV100 To FPGA From FPGA From “Cold” FPGA SW-1 SW-2

Flliper valve control circuit is based on 4 switches A +12 FV + B GND AB OPEN Valve with positive pulse CLOSE Valve with negative pulse Open Time MAX = 100 ms Close Time MAX = 100 ms Current = 150 mA Part List: 2 x Half Bridge Si4544 (ID = 6.5A, VDS = 30V) 1 x 2N-Mosfet Si4966 (ID = 7A, VDS = 20V)

UGBS interface to BOX-S Tasks: open the valves test the status of the valves monitor pressure and temperature sensor emergency open of safety valve without USCM intervention Redundancy: hot & cold (hot & hot will be evaluated against power budget) no duplication of control circuits on the same board

UGBS

UGFV interface to manifold valves Tasks: open/close the valves under USCM command open/close the valves under UGBC command pressure sensor output signal multiplexing to the USCM ADC input lines Redundancy: hot & cold (hot & hot will be evaluated against power budget) no duplication of control circuits on the same board

UGFV-XX

UGM modules 82 pressure sensors (honeywell 26PC-C) arranged in 16 modules (14 with 5 p.s. and 2 with 6 p.s.) The typical output signal from the sensor (Out+ / Out-) is in the ±100 mV range (±15psi) and is conditioned and multiplexed to be connected to the UGSCM ADC lines (0 to VDC) GND PC-C to USCM ADC-In From others modules Manifold module (6/5 pressure sensors) UGM module local to the sensors UGFV-xx board in the UGE crate Out+ Out- x6 1:8 AD620

UGM module

USCM UGFV-AC Backplane ADCBUS(1:6) UGFV ADC signals backplane USCM’ UGFV-AC’ UGFV-BD ADCBUS(1:6) UGFV-BD’ AIN(0:5) AIN(8:13) AIN(16:21) AIN(24:29) AIN(0:5) AIN(8:13) AIN(16:21) AIN(24:29)

UGpd-Box Power Supply Requirements Hot and Cold redundancy used 10 DC-DC Converters needed Operating Voltage (V) Normal Power (W) < Peak Power (W) < DC-DC Converter 2x CAEN S9025 ? LAMBDA or INTERPOINT ? 2x CAEN S9022 2x CAEN S9024 2x CAEN S9023 Total