Computing Labs CL5 / CL6 Multi-/Many-Core Programming with Intel Xeon Phi Coprocessors Rogério Iope São Paulo State University (UNESP)

MPC Lab Sessions Hands-on activities divided in topics - 2x ~3-hour sessions Learner proceeds from one topic to the next at his/her own speed First session – Starts with a live demo on how to access the remote system – Finishes with a high-performance test-drive, where the participant is guided tries to extract the maximum performance of a coprocessor. Second session – Provides extra coverage of introductory aspects of programming the Intel manycore coprocessor – Concludes with an example on how to improve the performance efficiency of applications developed for the Xeon Phi 2

Lab Session 1 (CL5) 1. Introduction to the Intel Xeon Phi Coprocessor – Overview of the hardware architecture – Overview of the system software and programming models 2. Compiling and running simple applications 3. High-performance Test-Drive 4. Running a basic N-body simulation (optional) 3

Lab Session 2 (CL6) 1. Task Parallelism with OpenMP and Cilk Plus – Overview of OpenMP – Overview of Cilk Plus 2. Intel MPI Programming Models 3. Using Intel Math Kernel Library (MKL) 4. Optimizing a real-world code example 4

Intel / Unesp Manycore Testing Lab A special remote system that allows faculty and students to work with computers with lots of cores One of the first manycore labs outside U.S. – Server donated by Intel  Intel Xeon Phi coprocessors  Suite of Intel's software development tools – Users  test the performance of their codes in a highly parallel system  are registered as guests into CSC user database (LDAP) – Authentication / authorization  controlled by digital certificates issued by ANSP Grid CA First results: hands-on activities at – INFIERI Summer School 2013 (University of Oxford) – Intel Software Conference 2013 (UNESP/SP and COPPE/RJ) – SBAC-PAD 2013 Paralell Programming Marathon 5

Intel / Unesp Manycore Testing Lab Host Server – 2x Intel Xeon processor, 8-core, 2.3 GHz (E5-2670) – 64 GB memory, 1+1 TB disk – 2 network links:  University network (commodity, shared)  High-speed optical network (dedicated) – 3x Xeon Phi 57-core, 1.1 GHz, 6 GB GDDR mem (3120A) Total number of cores – Xeon processors: 16 cores, 32 threads – Xeon Phi coprocessors: 171 cores, 684 threads 6

Intel Xeon Phi coprocessors portfolio 7

Formal Agreement with Intel 28/Aug/13HEP Workshop8

Formal Agreement with Intel 28/Aug/13HEP Workshop9