1MWSCAS-2002 HIGH PERFORMANCE CMOS REALIZATION OF THE THIRD GENERATION CURRENT CONVEYOR (CCIII) S. Minaei 1, M. Yıldız 1, H. Kuntman 2, S. Türköz 2 1.Doğuş University, Department of Electronics and Communication Engineering, 81010, Acıbadem, Kadıköy, Istanbul, TURKEY. 2. Istanbul Technical University, Faculty of Electrical and Electronics Engineering, Department of Electronics and Communication Engineering, 80626, Maslak, Istanbul.

MWSCAS ABSTRACT In this paper a new CMOS high performance dual-output realization of the third generation current conveyor (CCIII) is presented. The proposed CCIII provides good linearity, high output impedance at port Z and excellent input/output current gain. PSPICE simulation results using MIETEC 1.2  CMOS process model are included to verify the expected values. In this paper a new CMOS high performance dual-output realization of the third generation current conveyor (CCIII) is presented. The proposed CCIII provides good linearity, high output impedance at port Z and excellent input/output current gain. PSPICE simulation results using MIETEC 1.2  CMOS process model are included to verify the expected values.

MWSCAS INTRODUCTION ● Current conveyors and unity-gain amplifiers are widely used by analog designers: ●Signal processing ●Active network synthesis ●Recently third generation of this block has also been proposed by Fabre et al [3]. ●The third generation current conveyors (CCIIIs) can be considered as a current controlled current source with a unity gain.

MWSCAS High performance current mirrors are required in the structure of the CCIII to provide: High performance current mirrors are required in the structure of the CCIII to provide: –Good dynamic swing –High output resistance which enables cascadability. The main features of the CCIII are: The main features of the CCIII are: –Low gain errors (high accuracy) –High linearity –Wide frequency response.

MWSCAS In this paper, we propose a novel implementation of dual-output CCIII based on an improved active-feedback cascode current mirrors (IAFCCM). In this paper, we propose a novel implementation of dual-output CCIII based on an improved active-feedback cascode current mirrors (IAFCCM). The proposed CCIII is compared with the conventional CCIII proposed in [3] and cascode CCIII. It provides: The proposed CCIII is compared with the conventional CCIII proposed in [3] and cascode CCIII. It provides: –High output resistance at port Z and –High dynamic swing.

MWSCAS CIRCUIT DESCRIPTION The port relations of an ideal dual-output CCIII is shown in Figure 1. The port relations of an ideal dual-output CCIII is shown in Figure 1. The positive and negative signs define a positive and negative current-controlled conveyor. The positive and negative signs define a positive and negative current-controlled conveyor. Figure 1. Electrical symbol of the CCIII

MWSCAS The conventional third generation current conveyor is shown in Figure 2 [3]. The conventional third generation current conveyor is shown in Figure 2 [3]. Figure 2a. Conventional third generation current conveyor (CCIII). The conventional third generation current conveyor is shown in Figure 2a [3]. The conventional third generation current conveyor is shown in Figure 2a [3]. Figure 2b. Conventional (CCIII) core view from X and Y ports.

MWSCAS A major advantage of this CCIII is its simple structure. A major advantage of this CCIII is its simple structure. An important drawback of the conventional CCIII is the finite output resistance (Roz). An important drawback of the conventional CCIII is the finite output resistance (Roz). The Z+ output resistance of this current conveyor is, The Z+ output resistance of this current conveyor is, – Roz+ = (rds21)//(rds22) – where rdsi denotes the output resistance of the i’th transistor respectively. Third generation current conveyor using cascode current mirrors is shown in figure 3. Third generation current conveyor using cascode current mirrors is shown in figure 3. The cascode current mirrors between ports X-Y, X-Z+, and Y-Z- as shown in Figure 3. The cascode current mirrors between ports X-Y, X-Z+, and Y-Z- as shown in Figure 3. –Increase the accuracy of the current transformations in the CCIII.

MWSCAS The Z+ output resistance of the cascode CCIII is calculated as: The Z+ output resistance of the cascode CCIII is calculated as:  Roz+  (rds29 rds25 gm29)// (rds30rds26 gm30) Figure 3. Third generation current conveyor using cascode current mirrors.

MWSCAS To increase the output resistance we propose a new CCIII based on using improved active- feedback cascode current mirror (IAFCCM) [10] in the output stages of the conveyor. To increase the output resistance we propose a new CCIII based on using improved active- feedback cascode current mirror (IAFCCM) [10] in the output stages of the conveyor. The proposed CCIII is shown in Figure 4. The proposed CCIII is shown in Figure 4. The output resistance of the proposed CCIII is calculated as: The output resistance of the proposed CCIII is calculated as:  Roz+ = gm32 gm30 rds31 rds32 (rds30// rds28) //gm40 gm38 rds39 rds40 (rds38// rds34)

MWSCAS Figure 4. The proposed third generation current conveyor CCIII.

MWSCAS SIMULATION RESULTS AND COMPARISON The performance of the proposed CCIII shown in Figure 4, is verified by SPICE simulation program using, The performance of the proposed CCIII shown in Figure 4, is verified by SPICE simulation program using, MIETEC 1.2  m CMOS process model parameters MIETEC 1.2  m CMOS process model parameters PMOS transistor dimensions are W/L=720µm/2.4µm and, PMOS transistor dimensions are W/L=720µm/2.4µm and, NMOS transistor dimensions are W/L=240µm/2.4µm. NMOS transistor dimensions are W/L=240µm/2.4µm. The voltage supply used for the proposed CCIII is  2.5V. The voltage supply used for the proposed CCIII is  2.5V.  The main performances of the conventional, cascode and proposed CCIII are summarized in Table 1.  From Table 1 it can be seen that the performance of the proposed CCIII is improved in terms of, Linearity gain accuracy output resistance.

MWSCAS Figure 5. The relation between VX-VY for the proposed CCIII Figure 6. The relation between IX-IY-IZ for the proposed CCIII. Figure 7.The frequency response of the VX/VY Figure 8. The frequency response of the IZ+/IX and IZ-/IX

MWSCAS ParameterConventional CCIIICascode CCIIIProposed CCIII Dynamic swing V X -V Y -0.55V  0.6V-1.8V  1.9V-2  2.1 Dynamic swing I Z+ -I X -0.8mA  0.8mA-0.65mA  0.7mA-1mA  1mA Dynamic swing I Z- -I X -1mA  1mA-0.4mA  0.70mA-0.85mA  0.85mA V X /V Y accuracy I Z+ /I X accuracy I Z- /I X accuracy V X /V Y f -3dB 306MHz87MHz89MHz I Z+ /I X f -3dB 106MHz15MHz24.7MHz I Z- /I X f -3dB 83MHz10.2MHz14.7MHz Output resistance (R Z+ ) 18.2k  18M  5.59 G  Output resistance (R Z- ) 18.2k  17.9M  6.73 G  Offset15mV0.145mV0.1mV Settling time (0.1 percent) 100ns51ns17ns Power dissipation0.88mW1.37mW3.38mW Table 1. Circuit performances.

MWSCAS CONCLUSION The proposed circuit uses improved active- feedback cascode current mirrors (IAFCCM), which increases output resistance at port-Z. The proposed circuit uses improved active- feedback cascode current mirrors (IAFCCM), which increases output resistance at port-Z. The proposed circuit is compared with the conventional and cascode CCIIIs. The simulation results confirm high performance of the circuits in terms of The proposed circuit is compared with the conventional and cascode CCIIIs. The simulation results confirm high performance of the circuits in terms of –Linearity –Voltage gain accuracy –Current gain accuracy..

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