Design of a RISC Processor Compatible with ARM Instruction Set AHMET GÜRHANLI LAB: BL405 SUPERVISER: 陳中平 教授

OUTLINE General Architecture Inputs and Outputs Components Instructions Simulation Results Conclusion

GENERAL ARCHITECTURE

ARM multi-cycle instruction pipeline operation

Fetch Stage

Decode Stage Decode/Execute Pipeline Registers

Execute Stage

INPUTS & OUTPUTS

COMPONENTS

Register Bank

Program Status Register

ALU

Multiplier

The Enhancements We Made Shortening the Branch Process From 3 cycles to 2 cycles Fastening the Abort Entry Procedure

The Original Instruction Pipeline

Our Design

Abort Entry In the original design in case of an abort the running instruction is processed until the end, and then re-processed after abort interrupt. This may cause unnecessary stalls up to 16 cycles In our design processor can stop instruction execution immediately in case of a memory abort.

INSTRUCTIONS

Branch

Data Processing

ADD R1,R0,#15

ARM Data Processing Instructions

Multiply Rd = Rs*Rm Multiply Rd = Rs*Rm+Rn Multiply Accumulate

Multiply MUL R4,R2,R1

Multiple Transfer LDMIA R0!,{R5-R8}

SIMULATION RESULTS before simulation: memory [ 200] = xxxxxxxx before simulation: memory [ 201] = xxxxxxxx before simulation: memory [ 202] = xxxxxxxx before simulation: memory [ 203] = xxxxxxxx before simulation: memory [ 204] = xxxxxxxx before simulation: memory [ 205] = xxxxxxxx before simulation: memory [ 206] = xxxxxxxx before simulation: memory [ 207] = xxxxxxxx before simulation: memory [ 208] = xxxxxxxx before simulation: memory [ 209] = xxxxxxxx before simulation: memory [ 210] = xxxxxxxx before simulation: memory [ 211] = xxxxxxxx before simulation: memory [ 212] = xxxxxxxx before simulation: memory [ 213] = xxxxxxxx before simulation: memory [ 214] = xxxxxxxx before simulation: memory [ 215] = xxxxxxxx before simulation: memory [ 216] = xxxxxxxx before simulation: memory [ 217] = xxxxxxxx before simulation: memory [ 218] = xxxxxxxx before simulation: memory [ 219] = xxxxxxxx

SIMULATION RESULTS after simulation: memory [ 200] = after simulation: memory [ 201] = after simulation: memory [ 202] = after simulation: memory [ 203] = after simulation: memory [ 204] = after simulation: memory [ 205] = after simulation: memory [ 206] = after simulation: memory [ 207] = after simulation: memory [ 208] = after simulation: memory [ 209] = after simulation: memory [ 210] = after simulation: memory [ 211] = after simulation: memory [ 212] = after simulation: memory [ 213] = after simulation: memory [ 214] = after simulation: memory [ 215] = after simulation: memory [ 216] = after simulation: memory [ 217] = after simulation: memory [ 218] = after simulation: memory [ 219] =

CONCLUSIONS Architecture coding is almost finished. Simple synthesis of the design is successful. We will finish the design flow as soon as possible and make the design ready for tape- out.

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