Mugil Vannan H ST Microelectronics India Pvt. Ltd, Noida Test Coverage Analysis of Partial Scan SoCs using ATPG and Fault Simulation of Functional vectors using TetraMax: A Case Study Mugil Vannan H ST Microelectronics India Pvt. Ltd, Noida

Testability for Non-Scan Devices Full Scan designs rely on Tool generated ATPG vectors. Test Coverage of 99% not uncommon for Full-Scan Partial and Non-Scan rely on Functional Vectors and internal BIST techniques like Signature analysis using LFSR (Linear FeedBack Shift Register). But no real metric for the Stuck-At Coverage offered by these vectors. TetraMax Fault-Sim flow for Test Coverage improvement through External Vectors.

TetraMax Fault Simulation Flow Fault Simulation can be performed Stand Alone (Non-Scan) or in combination with ATPG (Partial and Full Scan) The flow Run Basic Scan ATPG for the Scan Part of the design. Save the uncollapsed fault list. Load the external vectors and perform a good machine simulation. Now, fault simulate the external vectors. TetraMax accepts vectors in variety of formats. We used WGL format. Some external vectors fail good machine simulation giving simulation miscompares. TetraMax Bug found (STAR 9000064596) Other reasons: Bad patterns, difference in simulation models.

TetraMax Fault-simulation Environment External Patterns are usually generated from logic Simulators which are ‘Event-Driven’. TetraMax is a Cycle-based simulator. Computes Steady state response of circuit at each cycle boundary. Does not propagate values through every gate. So, it cannot catch glitches. Is a ‘Zero Delay simulator’. But cycle based simulations are 10 to 100 times faster than Event driven simulations. Fault simulation environment should mimic the functional simulaiton environment. Analog blocks that affect pattern simulation cannot be declared as black boxes.

Memory Models ST7 functional test vectors are run from the RAM. The Address of the reset and interrupt routines are stored in the ROM. TetraMax compatible RAM and ROM behavioral models are necessary for fault simulation. TetraMax supports a very limited subset of verilog syntax. Supports only conventional memory blocks in the form of basic 2-D arrays. It is difficult to write decoding logic in case of segmented memory, where address is to be decoded. Needs structural implementation. So, even the TetraMax behavioral models are mostly structural.

Shadow Logic Detection TetraMax cannot detect faults in the shadow logic if the corresponding Analog blocks are defined as black boxes. We modeled RAM, ROM and ADC and were able to detect faults in the shadow of these blocks. The ADC Interface (Digital) is in the shadow of the ADC block. Shadow Logic Total Faults Initial Test Cov After Fault simultion ADC Interface 760 4.53% 61%

Test Coverage Vs Code Coverage Good statement or toggle coverage does not necessarily mean good test coverage. For a fault to be detected, it has to be both controlled and propagated to one of the primary ports of the DUT where it can be observed. Toggle coverage is concerned only with controllability of a node. Fault grading functional vectors is an effective method to weed out patterns that do not capture many production faults. Thus we can reduce the size of the production pattern set and also save on testing time per device. *

Coverage Improvement Results and Time Estimate

Conclusion Fault Grading can be used to improve the coverage of full scan and partial scan architectures by running a few functional vectors after the ATPG run. It is a good means to detect redundant functional vectors that have low fault detection capability. Fault Grading helps us write functional vectors aimed at faults in the design and bridge the gap between testing functionality and capturing stuck-at faults. Also there is a need for a waveform viewer. It is very tedious to debug full sequential patterns on the GSV (Graphical Schematic viewer). We can also have diagnosis capability for full-sequential patterns.