Faculty of Computer Science © 2006 CMPUT 229 Input and Output Devices Pooling and Interrupts.

Slides:



Advertisements
Similar presentations
Homework Reading Machine Projects Labs
Advertisements

Computer Architecture
I/O Organization popo.
Computer Architecture
Chapter 10 Input/Output Organization. Connections between a CPU and an I/O device Types of bus (Figure 10.1) –Address bus –Data bus –Control bus.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir.
I/O Unit.
CS-334: Computer Architecture
1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 3: Input/output and co-processors dr.ir. A.C. Verschueren.
FIU Chapter 7: Input/Output Jerome Crooks Panyawat Chiamprasert
Input-output and Communication Prof. Sin-Min Lee Department of Computer Science.
Interfacing. This Week In DIG II  Basic communications terminology  Communications protocols  Microprocessor interfacing: I/O addressing  Port and.
DIRECT MEMORY ACCESS CS 147 Thursday July 5,2001 SEEMA RAI.
COMP3221: Microprocessors and Embedded Systems Lecture 15: Interrupts I Lecturer: Hui Wu Session 1, 2005.
6-1 I/O Methods I/O – Transfer of data between memory of the system and the I/O device Most devices operate asynchronously from the CPU Most methods involve.
1 TK2633TK Microprocessor Architecture DR MASRI AYOB.
The Structure of the CPU
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
1 Interrupts INPUT/OUTPUT ORGANIZATION: Interrupts CS 147 JOKO SUTOMO.
680XX Hardware Interface Outline Goal Reading
Input-Output Problems L1 Prof. Sin-Min Lee Department of Mathematics and Computer Science.
Chapter 7 Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats.
9/20/6Lecture 3 - Instruction Set - Al Hardware interface (part 2)
1 COSC 3P92 Cosc 3P92 Week 11 Lecture slides Violence is the last refuge of the incompetent. Isaac Asimov, Salvor Hardin in "Foundation"
Group 7 Jhonathan Briceño Reginal Etienne Christian Kruger Felix Martinez Dane Minott Immer S Rivera Ander Sahonero.
2. Methods for I/O Operations
The computer system’s I/O architecture is its interface to the outside world. This architecture provides a systematic means of controlling interaction.
Chapter 7 Input/Output Luisa Botero Santiago Del Portillo Ivan Vega.
Interrupts. 2 Definition: An electrical signal sent to the CPU (at any time) to alert it to the occurrence of some event that needs its attention Purpose:
Chapter 10: Input / Output Devices Dr Mohamed Menacer Taibah University
MICROPROCESSOR INPUT/OUTPUT
Input/Output. I/O Initiation & Control  Transfer of data between circuitry external to the microprocessor and the microprocessor itself.  Transfer of.
Interrupts and DMA CSCI The Role of the Operating System in Performing I/O Two main jobs of a computer are: –Processing –Performing I/O manage and.
1 Input-Output Organization Computer Organization Computer Architectures Lab Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes.
Spring EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Advanced Computer Architecture Lecture 8 Project 3: memory agent Programmed.
1. Introduction 2. Methods for I/O Operations 3. Buses 4. Liquid Crystal Displays 5. Other Types of Displays 6. Graphics Adapters 7. Optical Discs 10/01/20151Input/Output.
© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Principles of I/0 hardware.
I/O Example: Disk Drives To access data: — seek: position head over the proper track (8 to 20 ms. avg.) — rotational latency: wait for desired sector (.5.
DMA Versus Polling or Interrupt Driven I/O
I/O management is a major component of operating system design and operation Important aspect of computer operation I/O devices vary greatly Various methods.
I/O Interfacing A lot of handshaking is required between the CPU and most I/O devices. All I/O devices operate asynchronously with respect to the CPU.
Dr Mohamed Menacer College of Computer Science and Engineering Taibah University CE-321: Computer.
COMPUTER ORGANIZATIONS CSNB123 NSMS2013 Ver.1Systems and Networking1.
Direct Memory Access (DMA) Microprocessors I -1. Topics to be discussed  Basic DMA Concept Basic DMA Concept  DMA pins and timing DMA pins and timing.
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
Input-Output Organization
Microprocessor. Interrupts The processor has 5 interrupts. CALL instruction (3 byte instruction). The processor calls the subroutine, address of which.
Modes of transfer in computer
L/O/G/O Input Output Chapter 4 CS.216 Computer Architecture and Organization.
The computer system’s I/O architecture is its interface to the outside world. This architecture provides a systematic means of controlling interaction.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU.
Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)
بسم الله الرحمن الرحيم MEMORY AND I/O.
 The Programmable Interrupt Controller (PlC) functions as an overall manager in an Interrupt-Driven system. It accepts requests from the peripheral equipment,
Lecture Overview Shift Register Buffering Direct Memory Access.
Direct Memory Access (DMA) Department of Computer Engineering, M.S.P.V.L. Polytechnic College, Pavoorchatram. A Presentation On.
Introduction to Exceptions 1 Introduction to Exceptions ARM Advanced RISC Machines.
I/O Systems Shmuel Wimer prepared and instructed by
Department of Computer Science and Engineering
Direct Memory address and 8237 dma controller LECTURE 6
I/O Memory Interface Topics:
Md. Mojahidul Islam Lecturer Dept. of Computer Science & Engineering
Md. Mojahidul Islam Lecturer Dept. of Computer Science & Engineering
Computer System Overview
COMP3221: Microprocessors and Embedded Systems
Chapter 13: I/O Systems.
Presentation transcript:

Faculty of Computer Science © 2006 CMPUT 229 Input and Output Devices Pooling and Interrupts

© 2006 Department of Computing Science CMPUT 229 I/O Fundamentals  Programmed data transfer –An instruction for each data transfer  Direct Memory Access (DMA) transfer –Processor requests transfer –DMA controller moves the data between I/O and memory Clements, pp. 412

© 2006 Department of Computing Science CMPUT 229 I/O Fundamentals Clements, pp. 412 Twisted pair Start bit Stop bit

© 2006 Department of Computing Science CMPUT 229 I/O Fundamentals Clements, pp. 413 Looks like a Memory location

© 2006 Department of Computing Science CMPUT 229 Memory-mapped I/O Clements, pp. 414

© 2006 Department of Computing Science CMPUT 229 Memory-mapped I/O  Each memory-mapped I/O device occupies at least two memory locations: –A location for the data input or data output –A location for the status byte associated with the port  Example –Assume the following semantics for bit 0 of the status byte: 1: port is ready for data 0: port is busy

© 2006 Department of Computing Science CMPUT 229 Pooling FORI = 1 TO128 REPEAT Read Port_status_byte UNTIL Port_not_busy Move data from Table i to output_port ENDFOR Clements, pp. 415

© 2006 Department of Computing Science CMPUT 229 Pooling PORTDATAEQU$ Port address PORTSTATEQU$ Port status byte COUNTEQU128Size of block to output * ORG$002000Start of data area TABLEDS.B128 * ORG$ MOVE#COUNT, D1Set count in D1 LEATABLE, A0A0 points to table in memory LEAPORTDATA, A1A1 points to data port LEAPORTSTAT, A2A2 points to port status byte LOOPMOVE.B(A0)+, D0Get byte from table WAITMOVE.B(A2), D2 REPEAT Read port status AND.B#1, D2 Mask to extract lsb BEQWAIT Until port is ready MOVE.BD0, (A1)Store data in peripheral SUB#1, D1Decrement loop counter BNELOOPRepeat until COUNT = 0 Clements, pp. 415 Pooling Loop

© 2006 Department of Computing Science CMPUT 229 Interrupt Organization Clements, pp. 416

© 2006 Department of Computing Science CMPUT 229 Interrupt Sequence Clements, pp. 417

© 2006 Department of Computing Science CMPUT 229 Interrupt Sequence Clements, pp. 417

© 2006 Department of Computing Science CMPUT 229 Interrupt Sequence Clements, pp. 417

© 2006 Department of Computing Science CMPUT 229 Interrupt Sequence Clements, pp. 417

© 2006 Department of Computing Science CMPUT 229 Interrupt Sequence Clements, pp. 417

© 2006 Department of Computing Science CMPUT 229 Prioritized Interrupts  The 68K supports seven interrupt request inputs: –IRQ7 is the most important also called a non-maskable interrupt request –IRQ1 is the least important  The seven interrupt requests are encoded in three interrupt request inputs: –IPL0, IPL1, and IPL2

© 2006 Department of Computing Science CMPUT 229 Masking Interrupts  The 68K has an interrupt mask that determines which interrupt requests are enabled –This mask is formed three bits (I2, I1, I0) of the processor status register –When the 68K services an interrupt, the mask is changed to match the level of the interrupt being serviced Thus lower level interrupts are disabled until the current one is serviced

© 2006 Department of Computing Science CMPUT K Interrupt Structure Clements, pp

© 2006 Department of Computing Science CMPUT K Status Word Clements, pp. 419

© 2006 Department of Computing Science CMPUT 229 Vectored Interrupts  How the processor finds out which device requested an interruption: –Polling: test sequentially each possible interruptor –Vectorized: The interruptor identifies its own interrupt handling routine

© 2006 Department of Computing Science CMPUT 229 Interface polling: Memory-mapped data and status port Clements, pp. 419

© 2006 Department of Computing Science CMPUT 229 Responding to Vectored Interrupt Clements, pp. 420

© 2006 Department of Computing Science CMPUT 229 Daisy-chaining  There 256 interrupt vector numbers –But the 68K supports only seven levels of interrupt  Daisy-chain links several peripherals together in a line.  Devices closer to the CPU have more chances of having their interrupts acknowledged.

© 2006 Department of Computing Science CMPUT 229 Daisy-Chain of I/O Devices Clements, pp. 421

© 2006 Department of Computing Science CMPUT 229 Direct Memory Access  Transfer data from a peripheral and memory  DMA grabs the data and address bus  Releases the processor from executing many instructions to transfer the data.

© 2006 Department of Computing Science CMPUT 229 DMA Protocol Clements, pp. 423

© 2006 Department of Computing Science CMPUT 229 DMA Protocol Clements, pp. 423

© 2006 Department of Computing Science CMPUT 229 DMA Protocol Clements, pp. 423

© 2006 Department of Computing Science CMPUT 229 DMA Protocol Clements, pp. 423

© 2006 Department of Computing Science CMPUT 229 DMA Protocol Clements, pp. 423

© 2006 Department of Computing Science CMPUT 229 Direct Memory Access Clements, pp. 422

© 2006 Department of Computing Science CMPUT 229 Direct Memory Access Clements, pp. 422

© 2006 Department of Computing Science CMPUT 229 DMA Operating Modes  Burst Mode –DMA seizes the bus and keep it until the data transfer is completed  Cycle Stealing Mode –DMA operations are interleaved with normal memory accesses. –Called transparent DMA

© 2006 Department of Computing Science CMPUT 229 DMA by Cycle Stealing