© 2000 Morgan Kaufman Overheads for Computers as Components CPUs zInput and output mechanisms zInterrupts zMemory management unit (MMU) zCache mechanism zCPU performance: Pipelining zCPU power consumption

© 2000 Morgan Kaufman Overheads for Computers as Components I/O devices zUsually includes some non-digital components. zTypical digital interface to CPU: CPU Status/control registers Data registers mechanism Programmable device: e.g., A/D converter bank, serial port, …

© 2000 Morgan Kaufman Overheads for Computers as Components Application: 8251 UART zUniversal asynchronous receiver transmitter (UART): provides serial communication, e.g., serial port connection on PC’s z8251 functions are integrated into a standard PC interface chip. zAllows many communication parameters to be programmed.

© 2000 Morgan Kaufman Overheads for Computers as Components Serial communication zCharacters are transmitted separately: time bit 0bit 1bit n-1 no char Start Bit: 0 Stop bit: 1... One character Period= 1/baud rate

© 2000 Morgan Kaufman Overheads for Computers as Components Serial communication parameters zBaud (bit) rate. zNumber of bits per character: 5-8 zParity/no parity. zEven/odd parity. zLength of stop bit (1, 1.5, 2 bits). zTransmitter/Receiver Ready/Empty: Pin indicating status of Receiver/Transmitter 8251 D0-D7 TxD RxD R/W CS TxRdy RxRdy C/D Control/data Port selection other

© 2000 Morgan Kaufman Overheads for Computers as Components 8251 CPU interface CPU 8251 Status reg (8 bit) Data reg (8 bit) serial port xmit/ rcv

© 2000 Morgan Kaufman Overheads for Computers as Components Programming I/O zTwo ways that microprocessors can support I/O: yspecial-purpose I/O instructions; ymemory-mapped load/store instructions.  Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O. zI/O instructions do not preclude memory- mapped I/O, i.e., can use memory map as well.

© 2000 Morgan Kaufman Overheads for Computers as Components ARM memory-mapped I/O zDefine location for device: DEV1 EQU 0x1000 zRead/write code: LDR r1,#DEV1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write 8 to device Pseudo-op to define DEV1

© 2000 Morgan Kaufman Overheads for Computers as Components Peek and poke: Use pointers to manipulate I/O zHigh level language interface: int peek(char *location) { return *location; }  #define DEV1 0x1000 int dev_status; dev_status = peek(DEV1); //read device register

© 2000 Morgan Kaufman Overheads for Computers as Components … Peek and poke  void poke(char *location, char newval) { (*location) = newval; }  EXAMPLE: poke (DEV1, 8); //write 8 to device register

© 2000 Morgan Kaufman Overheads for Computers as Components Busy/wait input/output zDevices are typically slower than the CPU: e.g., if we start writing a character before the device has finished with the first one, there may be a problem … z Asking I/O if it has finished by reading a bit in the status register: yBusy waiting on a status bit yPeriodically polling the status bit (with no waiting)

© 2000 Morgan Kaufman Overheads for Computers as Components Example: Write a sequence of characters to an output device  device has status/character registers #define OUT_CHAR 0x1000 //character register address #define OUT_STATUS 0x1001 //status register address char *mystring=``Hello’’; //pointer to a char string char *current_char; /* pointer to current position */ current_char = mystring; while (*current_char != ‘\0’) { poke(OUT_CHAR,*current_char); while (peek(OUT_STATUS)!= 0) ; //1=busy current_char++; }

© 2000 Morgan Kaufman Overheads for Computers as Components Simultaneous busy/wait input and output  Repeatedly read a character from an input device and write it to an output device. #define IN_DATA 0x1000 //define addresses #define IN_STATUS 0x1001 #define OUT_DATA 0x1102 #define OUT_STAT 0x1103 while (TRUE) { /* read */ while (peek(IN_STATUS) == 0) ; achar = (char) peek(IN_DATA); Input device sets IN_STATUS=1 when a new char arrives

© 2000 Morgan Kaufman Overheads for Computers as Components … Simultaneous busy/wait input and output /* write */ poke(OUT_DATA,achar); poke(OUT_STATUS,1); /* turn on device */ /* wait until done */ while (peek(OUT_STATUS) != 0); } /* end of while(TRUE) */

© 2000 Morgan Kaufman Overheads for Computers as Components Interrupt I/O zBusy/wait is very inefficient. yCPU can’t do other work while testing device, e.g., can control other I/O or do computation yHard to do simultaneous I/O. zAlternative: Polling with no busy waiting, interrupts zInterrupts allow a device to change the flow of control in the CPU. yCauses subroutine call to handle device.

© 2000 Morgan Kaufman Overheads for Computers as Components Interrupt interface CPU Control/ status reg data reg mechanism PC intr request intr ack data/address IR Asserted by I/O when it wants service from CPU Asserted by CPU

© 2000 Morgan Kaufman Overheads for Computers as Components Interrupt sequence zDevice asserts interrupt line. zCPU acknowledges request. zCPU calls handler (could be vectored int’pt). zSoftware processes request. zCPU restores state to foreground program.

© 2000 Morgan Kaufman Overheads for Computers as Components Interrupt behavior zBased on subroutine call mechanism. zInterrupt forces next instruction to be a subroutine call to a predetermined location. yReturn address is saved to resume executing foreground program (the program that runs when no interrupt is being handled)

© 2000 Morgan Kaufman Overheads for Computers as Components Interrupt physical interface zCPU and device are connected by CPU bus (Data/Address/Control). zCPU and device handshake: ydevice asserts interrupt request; yCPU asserts interrupt acknowledge when it can handle the interrupt.

© 2000 Morgan Kaufman Overheads for Computers as Components Example: character I/O handlers  Repeatedly read char from input and write it to output char achar; /*for passing to foreground program */ char gotchar; /* signalling a new character */ // Interrupt routine void input_handler() { achar = peek(IN_DATA); /* get char */ gotchar = TRUE; /* signal to main() */ poke(IN_STATUS,0); /* reset status for next transfer */ }

© 2000 Morgan Kaufman Overheads for Computers as Components Example: Interrupt-driven main program main() { while (TRUE) { if (gotchar) { poke(OUT_DATA,achar); gotchar = FALSE; }

© 2000 Morgan Kaufman Overheads for Computers as Components Problems with interrupts zRace conditions int position, velocity; void f1(){ position = peek(POS_DEV_ADDRESS); velocity = peek(VEL_DEV_ADDRESS); } void f2(){ while(1) { plot(position*POS_SCALE_FACTOR); plot(velocity*VEL_SCALE_FAC); } This code is run by a periodic interrupt line (ISR) Running as a main program

© 2000 Morgan Kaufman Overheads for Computers as Components … interrupts zWhat if interrupts are disabled in f2( )?  increases interrupt latency zInterrupt vs polling: Interrupt latency (ex. 60 micro-sec), polling a register (ex. 6 micro-sec)  FAST DEVICE: poll, SLOW DEVICES: interrupt zConvert periodic interrupts to periodic tasks

© 2000 Morgan Kaufman Overheads for Computers as Components Debugging interrupt code- in assembly programming zWhat if you forget to change registers? yForeground program can exhibit mysterious bugs, e.g., if a register is not properly restored in the interrupt handler yBugs will be hard to repeat---depend on interrupt timing.

© 2000 Morgan Kaufman Overheads for Computers as Components Sources of interrupt overhead zHandler execution time. zInterrupt mechanism overhead: branch penalty zRegister save/restore. zPenalties related to the specific architecture: pipeline/cache … zCoding the interrupt handler in assembly may resolve some of the issues, e.g., more efficient use of registers

© 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupts zARM7 supports two types of interrupts: yFast interrupt requests (FIQs): Takes priority over IRQ yInterrupt requests (IRQs). zInterrupt table starts at location 0 (bottom memory address). zInterrupt table contains subroutine calls to appropriate handlers.

© 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupt procedure zCPU actions: ySave PC. Copy CPSR to SPSR (Saved PSR) yForce bits in CPSR to record interrupt. yForce PC to the appropriate interrupt vector. zHandler responsibilities when leaving ISR: yRestore proper PC. yRestore CPSR from SPSR. yClear interrupt disable flags.

© 2000 Morgan Kaufman Overheads for Computers as Components ARM interrupt latency zWorst-case latency to respond to interrupt is 27 cycles zBest interrupt latency: 4 cycles NEXT  CPU & CACHE, MMU