4 Linking the Components

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.1 This chapter focuses on how the hardware layer components are physically connected and how the operating system layer communicates with the hardware layer.

© 2005 Pearson Addison-Wesley. All rights reserved The Bus Internal components are linked by a bus Bus types –Processor bus –Memory bus –Cache bus –Standard I/O bus –Local I/O bus PCI ISA

© 2005 Pearson Addison-Wesley. All rights reserved Word Size Computer designed around word size Word size affects: –processing speed –memory capacity –precision –instruction set size –cost

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.2 A machine cycle. a. The instruction control unit sends a fetch command to memory.

© 2005 Pearson Addison-Wesley. All rights reserved b. The memory controller copies the contents of the requested memory location onto the bus.

© 2005 Pearson Addison-Wesley. All rights reserved c. The instruction moves over the bus and into the instruction register.

© 2005 Pearson Addison-Wesley. All rights reserved d. The arithmetic and logic unit executes the instruction in the instruction register.

© 2005 Pearson Addison-Wesley. All rights reserved e. The arithmetic and logic unit sends a fetch command to memory.

© 2005 Pearson Addison-Wesley. All rights reserved f. The memory controller copies the contents of the requested memory location onto the bus and the data value flows into a work register.

© 2005 Pearson Addison-Wesley. All rights reserved Computer Architecture The relationships among a computer’s components.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.3 Most microcomputers are constructed around a motherboard.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.4 A schematic drawing of a motherboard highlighting the slots.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.5 Memory, peripherals, and secondary storage devices are added to the system by plugging the appropriate board into an open slot.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.6 With single-bus architecture all the components are linked by a common bus.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.7 An interface board translates between internal and external data forms.

© 2005 Pearson Addison-Wesley. All rights reserved Ports and Controllers Port (hardware) –A connection point for a peripheral –Serial port –Parallel port Controller –An interface board chip –Controls the data transfer process Peripheral to/from memory Memory to/from processor

© 2005 Pearson Addison-Wesley. All rights reserved External Buses USB – Universal serial bus SCSI – Small computer system interface –Pronounced “skuzzy” Port links one device or external bus Bus can link numerous devices

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.8 On a mainframe, device- independent functions are assigned to a channel and device-dependent functions are assigned to an I/O control unit.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.9 Most mainframes use multiple-bus architecture. a. The main processor starts an I/O operation by sending a signal to the channel.

© 2005 Pearson Addison-Wesley. All rights reserved b. The channel assumes responsibility for the I/O operation and the processor turns its attention to another program.

© 2005 Pearson Addison-Wesley. All rights reserved c. The channel sends an interrupt to the processor to signal the end of the I/O operation.

© 2005 Pearson Addison-Wesley. All rights reserved The Hardware/Software Interface Primitive –A physical operation performed by an interface or a peripheral device. Open –The process of initially establishing a link to a peripheral device.

© 2005 Pearson Addison-Wesley. All rights reserved Logical and Physical I/O Logical I/O –The programmer’s view of I/O. Physical I/O –The act of physically transferring a unit of data between memory and a peripheral device. Access Method –A subroutine that performs application- dependent portions of an I/O operation.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.10 A programmer’s logical I/O request is converted to the appropriate physical I/O operations by the operating system.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.11 Some mainframes assign application-dependent portions of the logical-to-physical translation process to access methods.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.12 The access method is added to the load module at load time.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.13 The process of converting a logical I/O request to primitive physical commands on a mainframe.

© 2005 Pearson Addison-Wesley. All rights reserved Figure 4.14 Microcomputers use device drivers as part of the logical-to-physical I/O conversion process.