Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Slides:

Advertisements

Similar presentations

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Fundamentals with PLD Programming.

Advertisements

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.

ECE 272 Xilinx Tutorial. Workshop Goals Learn how to use Xilinx to: Draw a schematic Create a symbol Generate a testbench Simulate your circuit.

XILINX ISE 9.1/9.2. To Get Familiar with the Environment How to start an FPGA project How to target your design to particular type of FPGA How to describe.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Fundamentals Tenth Edition Floyd.

ECE 331 – Digital System Design Basic Logic Functions, Truth Tables, and Standard Logic Gates.

EET 1131 Unit 4 Programmable Logic Devices  Read Kleitz, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.

ECE 448: Spring 12 Lab 4 – Part 2 Finite State Machines Basys2 FPGA Board.

Introduction to Basys 2. Switches Slide switchesPush button switches.

Figure 1.1 The Altera UP 3 FPGA Development board

© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.

Dr. Konstantinos Tatas ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Fundamentals Tenth Edition Floyd.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

Experiment #3A: Introduction to Function Reduction, Function Forms, and VHDL Implementation CPE 169 Digital Design Laboratory.

ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.

XOR and XNOR Logic Gates. XOR Function Output Y is TRUE if input A OR input B are TRUE Exclusively, else it is FALSE. Logic Symbol  Description  Truth.

Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.

Xilinx and Nexys2 Tutorial Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University, Houston, TX.

Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.

Comments on Lab #4 Annotating Timing Diagrams Draw viewer’s attention to the points you are trying to show / verify –Important output states glitch or.

© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.

1 Introduction to Xilinx ISL8.1i Schematic Capture and VHDL 1.

Basic Logic Operations and Standard Logic Gates (Lecture #1) ECE 331 – Digital System Design.

Sequential Arithmetic ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

1 Introduction to Xilinx ISL8.1i & 11.1 Schematic Capture 1.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”

Logic Gates Shashidhara H S Dept. of ISE MSRIT. Basic Logic Design and Boolean Algebra GATES = basic digital building blocks which correspond to and perform.

Boolean Logic and Circuits ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.

Lecture #3 Page 1 ECE 4110–5110 Digital System Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.HW#2 assigned Due.

Introductory project. Development systems Design Entry –Foundation ISE –Third party tools Mentor Graphics: FPGA Advantage Celoxica: DK Design Suite Design.

Introduction to FPGA Tools

Digital Fundamentals Floyd Chapter 3 Tenth Edition

ECE 2372 Modern Digital System Design Section 4.8 Xilinx Schematic Capture Simulation Tutorial.

Introduction to ECE 255 Lab Cheng Cheng, Teaching Assistant Department of EECS University of Tennessee.

COE4OI5 Engineering Design Chapter 1: The 15 minutes design.

11 EENG 1920 Introduction to VHDL. 22 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Introduction to Labs Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Basic Logic Operations and Standard Logic Gates [Lecture:1] Instructor: Sajib Roy Lecturer, ETE, ULAB ETE 204 – Digital Electronics.

Introduction ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

Boolean Algebra ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

How to use ISE Dept. of Info & Comm. Eng. Prof. Jongbok Lee.

Introduction to the FPGA and Labs

EET 1131 Unit 4 Programmable Logic Devices

EGR 2131 Unit 4 Combinational Circuits: Analysis & Design

Digital Fundamentals Floyd Chapter 3 Tenth Edition

Eng. Mai Z. Alyazji October, 2016

Engr. Micaela Renee Bernardo

Using Xilinx ChipScope Pro Tools

A tutorial guide to start with ISE

ECE 331 – Digital System Design

ECE 4110–5110 Digital System Design

Basic Digital Logic Basic Gates

Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

Elec 2607 Digital Switching Circuits

Week 5, Verilog & Full Adder

Digital Fundamentals Floyd Chapter 3 Tenth Edition

LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial”

Founded in Silicon Valley in 1984

XOR Function Logic Symbol  Description  Truth Table 

FIGURE 5-1 MOS Transistor, Symbols, and Switch Models

Eng. Ahmed M Bader El-Din October, 2018

Presentation transcript:

Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

311_032 Exclusive-OR (XOR)

XOR Theorems 311_033

Equivalence 311_034

Equivalence (XNOR) 311_035

6 Project 1  Combinational Circuit Analysis Determine input/output relationship of function Boolean Equation Truth Table Implement logic circuit with FPGA Schematic capture design tools Test circuit to verify operation Project Report  Teams of 2 persons

311_037 Xilinx ISE Design Suite  Enter description of logic circuit Schematic editor VHDL  Use a logic synthesizer to generate a netlist  Use implementation tools to map logic gates and interconnections into the FPGA  Generate a bitstream programming file  Configure device Download the bitstream to the FPGA chip

or Schematic 8311_03

9

10 New Project  File → New Project Project Name Demo1 Project Location C:\xxx\xxx Top-Level Module Type Schematic Device Family Spartan3E Device XC3S100E Package TQ144 (BASYS) CP132 (BASYS 2) Speed Grade -5

311_0311 New Source  Project → New Source Schematic Demo1  Schematic Editor Symbols Category list Symbol list Drawing area Tools Add wire Add I/O marker

add wire add I/O marker 12311_03

13 Demo1 Schematic  Categories Logic  Symbols and2 and3 inv or2  Add wires Point to point Stubs  I/O Markers Input marker Output marker Rename Port

Switches LEDs FPGA 14311_03

15 FPGA Pins

311_0316 Constrain the Design  User Constraints → I/O Pin Planning – Pre-Synthesis Implementation Constraints File Demo1.ucf PlanAhead I/O Ports  Site I/O NameLocationBASYSBASYS 2 XSW2P29 K3 YSW1P36 L3 ZSW0P38 P11 XYLD1P14 M11 FLD0P15 M5

311_0318 Synthesize & Implement  Synthesize Design  Implement Design  Generate Programming File

311_0319 BASYS Configuration Set to ROM

311_0320 Configure Device  Configure Device (Adept) Initialize Chain XCF02S (PROM) demo1.bit Program Cycle Power (Reset)

311_0321

311_0322 Test the Design XYZ F 0 1 XY

311_0323 Project Report  Cover Sheet Project Name/Number Authors Professor’s Initials  Objectives  Discussion Boolean Equation Truth Table Circuit Schematic  Conclusion Test Results