A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC Converters A-VLSI class presentation Adopted from isscc Presented by: Siamak Mehrnami

2 Outline ●Integrated DC-DC converters ●Linear regulator with digital control ●Implementation details ●measurements ●Conclusions

3 Integrated DC-DC Converters ●Demonstrated at 100MHz, η=87.7% Ref.: [3]

4 Problem: Low Input Voltage ●The CMOS process limits the DC-DC converter input voltage to V Ref: [1]

5 Doubling of Input Voltage Range ●V IN is across two transistors in series ●Need a ½-rail linear regulator Ref.: [4]

6 High tension power delivery through implicit voltage conversion ref:[2] 2V DD system 3V DD system 

7 Auxiliary Regulator Requirements ●Calculate Figure of Merit –single value to measure performance Ref:[1]

8 Auxiliary Regulator Figure of Merit ●Best known regulator had FOM=22ps –Rajapandian, et al., 2005 ISSCC, p. 298 ●Need same speed at 3X lower power ref:[1]

9 Traditional Linear Regulators ●Class-A buffer has poor slew rate ●Class-AB buffer degrades stability ref:[1]

10 Regulator with Digital Control ●Digital buffers (inverters) are perfect class- AB circuits, fast and low power ref:[1]

11 Push-Pull ½-Rail Regulator ref:[1]

12 Template Cell Design for Matching ref:[1]

13 Customized Inverter Cells ref:[1]

14 Floorplan of Matched Inverters ref:[1]

15 Regulator Test Chip in 90nm CMOS ref:[1]

16 Input-Output DC Characteristic ref:[1]

17 Output DC Characteristic ref:[1]

18 Load Step Response (5ns/div) ref:[1]

19 Performance Comparison ref:[1]

20 Conclusions ●Digital buffers (inverters) are more power-efficient than analog buffers ●Achieved 3.64X lower quiescent current at 28% slower response –FOM is 2.84X better than the prior art ●The power bottleneck moved from the analog buffer to the error amplifier –matching requirements influence transistor sizes and the quiescent current ref:[1]

21 References: ●1-P.Hazucha, “A Linear Regulator With Fast Digital Control For Biasing Integrated DC-DC Converters” ISSCC dig. tech. papers 29.2 feb.2006 ●2-S. Rajapandian, et al., “High-Tension Power Delivery- Operating 0.18µm CMOS Digital Logic at 5.4v,” ISSCC dig. Tech. papers,pp ,Feb., 2005 [page 6] ●3- Hazucha, et al., 2004 VLSI Symposium, p ●4-Xiao, et al., 2004 ISSCC, p. 280.