A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8) Speaker: Bing-Yu Hsieh MediaTek Inc., Hsin-Chu, Taiwan Authors: Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho

Outline Overview System Architecture Solutions for Low Power Issue Performance Comparison Summary

Overview Highly Integrated Commercial Application  Integrated Analog Front-End  Built-in 1.5Gb/s SATA PHY  On-Chip Write Strategy Generator  PRML Read Channel  Low Power Control Supports Multiple Format of Discs  CD/DVD-dual/DVD-RAM Record/Playback Operation Speed up to 56xS/18xS/16xS

System Architecture of FMSOC Pick-up Spindle

ARCHITECTURE RTL BACK-END Optimization Efficiency Solutions for Low Power Issue Efficient DRAM Access Adaptive Clock Control Multiple Clock Design Clock Suppression and Gating Voltage Partition Reduce Clock Buffer

Efficient DRAM Access - Bandwidth Large DRAM B.W. Requirement  DRAM is shared to multiple functions DRAM Access Efficiency  Performance Index: Ave. cycle # to access each word  Dominated by the times of DRAM Row Addr. Change

Efficient DRAM Access - Recursive Encode

Adaptive Clock Control - Background Data Rate of Optical Storage Varies with:  Rotation Speed  Radius of the Access Point Numerical Controlled Oscillator  Adaptive Control with Linear Steps

Adaptive Clock Control - Architecture Automatically adjust system clock with linear increments according to a throughput rate indicator

Adaptive Clock Control - Performance 9.2 DVD Read Speed (unit: xS) S y s t e m C l o c k F r e q. ( u n i t : M H z ) MHz 56MHz 67MHz 73MHz Adaptive Freq. Fixed Freq. (70.4mA) (81.5mA) (90.1mA) (94.4mA) (Digital Core Current)

Chip Micrograph

Chip Specification Technology 0.18  m CMOS 1P6M Supply Voltage1.8V Core, 3.3V Analog & I/O Core Area27.5 (5.4x5.1) mm 2 Transistor Counts~10M Max. Working Freq.471MHz Package216 LQFP Power Consumption 874mW DVD-R/RW/RAM 16xS W 772mW DVD-R/RW/RAM 16xS R 692mW CD 56xS W 664mW CD 56xS R

Comparisons of the Chip Performance

Summary Performance  Single Chip SoC with CD/DVD-dual/RAM Operation Speed up to 56xS/18xS/16xS Integration  SATA, WSG, PRML, Analog Front-End Integration 0.18  m CMOS with 27.5 mm 2 die size 16xS DVD playback Architectural Optimization for Low Power  Recursive Parity Encode  Adaptive Clock Control