LSST Electronics Review – BNL, January LSST Electronics Review BNL January Power & Voltage Plan R. Van Berg Electronics Mini-Review January 26 th, 2012

LSST Electronics Review – BNL, January Outline – Power Supplies for the RTMs Overview – Power Distribution System Power needs –FEB –RCC Vendor specific voltages –ITL –E2V Sequencing Protection

LSST Electronics Review – BNL, January Estimated Power Needs (LCA-275) – Science Rafts Peak Total Power (W) Sub-Assembly / ComponentQtyPower/ UnitPeak PowerQuiet PowerDuty CycleAvg Power Sci Raft Sensor Ass'y (RSA) CCD's Clock power /91.5 Output Amp power Raft Plate trim heaters Sci Front End Board (FEB) ASPIC /911.1 SCC / CCD Current Source Regulators /95.2 Sci Raft Ctl Crate (RCC) Back End Board (BEB) ADCs /91.8 Diff Amps /975.3 Power regulators CPLD etc Raft Control Module (RCM) Raft Control Module board

LSST Electronics Review – BNL, January Power Control & Monitoring – Design Concept for the Power Distribution System (PDS) Commercial AC components (filters, distribution) Commercial AC  48V converter Custom, isolated, 48V  DC converters for each load (rafts, HCUs, others) – full monitoring of I & V for each load Individual control of each load Located outside cryostat in UT Accessible during day Power fed through flange Independent supply each RTM

LSST Electronics Review – BNL, January Power Distribution System Location – Cabling Route Crates house support electronics in the Utility Trunk – in a volume that can be accessed within a single day shift for field replacement –Power regulators – custom and commercial –Opto converters –Timing and control fanout –Network switch(es) –Hardware Control Units (small computers) for CCS –Dedicated controllers (gauges, motors,…) Cabling harnesses and single cables –Cryostat to Crates – Raft power, data, timing –Sensors and operators in UT and CB to crates – power, control

LSST Electronics Review – BNL, January Raft Power Card Powers one to three RTMs (TBD) DC-DC converters to go from 48V DC “mains” to required levels Additional level of linear regulation in PDS for all sensitive voltages Each supply for each RTM is independent with independent supply and return lines (control is via isolated connections) Typical voltages – (note this is at less than 30W per FEC + 20W per RCC average power) –+7V for analog on FEB (one more linear regulation stage on FEB) – becomes +5V –+7V for CABAC on FEB – becomes +5V –+7V for digital on BEB / RCM – becomes +5; +3.5; +2.5; +1.8V –+35V for biases (CABAC) – adjusted on BEB –+12V for clock high levels (CABAC) adjusted on BEB –-70V for CCD substrate bias (e2V version) only adjusted at PDS

LSST Electronics Review – BNL, January CCD Voltage Requirements OD & Biasese2v CCD250ITL/STA1920AHPK S exposereadouterase Back substrateBS-70BB-10VBB50300,2 Front substrateFS0SUB0VGR000 GuardGD30SC Output DrainVOD30OD27VOD Output GateVOG2OG-2VOG-5 Reset DrainVRD18RD15VRD Test inject source----VISV Test inject gate----VIGV000 ClocksHILOHILOHILO erase Parallel Serial100, Reset Gate Summing Well Transfer Gate Capacitances (estimated) Parallel per phase64nFunavailable25nF(2K x 1K device) Serial per phase320pFunavailable50pF RGunavailable 10pF SW----10pF TG pF baseline

LSST Electronics Review – BNL, January FEB Voltages ASPIC power - +5V – local linear regulation from the PDS supplied +6-7V linear Vref +2.5V for ASPIC and ADCs - generated on BEB CABAC power – –Logic +5V (local linear regulation) –Bias +30V (OD [2 mA per CCD output], other biases at  A – from BEB DAC –Clock upper +12 (from DAC on BEB) –Clock lower 0-+1V (from DAC on BEB) OS current source fed from CABAC OD output

LSST Electronics Review – BNL, January RCC Voltages +5V analog, local linear regulator for ADCs and Diff Amps +5V analog, local linear regulator for DACs +35V and +15V inputs to BEB DACs to provide CABAC +5V digital for LVDS drivers, SPI devices Pass through of -70V for CCD substrate bias Digital supplies for FPGA on RCM – separate local regulation from +7V digital –+5V digital for FPGA –+3.3V digital for FPGA –+1.8V digital for FPGA

LSST Electronics Review – BNL, January Sequencing PDS is designed to allow software sequencing on power up or power down – e.g. –Turn on digital power –Configure FPGA –Test RCM digital behavior –Turn on some analog power –Further tests –Turn on all power –Verify operation –Full focal plane or raft by raft Emergency sequencing is not yet a requirement but we have not yet done a complete hazard analysis (this is somewhat vendor dependent) If any voltage sequence hazards are shown to exist we need to design a hardware protection scheme to prevent any dangerous relative potentials from happening (e.g. diodes)

LSST Electronics Review – BNL, January Protection Overvoltage and overcurrent built into PDS Raft Power Cards (hard coded limits) Very limited energy in each separate supply Fusing – makes sense on Raft Power Card for higher current supplies but not feasible for low current supplies (e.g. substrate bias) - NOTE that fuses are not allowed inside the cryostat (contamination worry)

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