Optical I/O Technology for Chip-to-Chip Digital VLSI Ian Young Intel Fellow Director, Advanced Circuits and Technology Integration Logic Technology Development Feb 23 rd 2004

2 What are We Announcing? Intel has made significant progress demonstrating the feasibility of optical chip-to-chip interconnect at data rates over 1 Giga-Transfers per second. Optical chip-to-chip interconnect may offer a faster, cheaper, better alternative to metal-based data buses between CPU and it’s supporting chips The demonstration was done with 0.18  m-CMOS transceiver, with on-chip laser drivers, input amps, and self-test features. The transceiver chip is integrated with the optical emitters, detectors, and wave-guides in a hybrid package This optical I/O implementation is highly compatible with CPU architecture, process, and packaging This announcement is a progress report from Intel’s Component’s Research Lab. Intel has not made a determination on product plans based upon these results.

3 Why is this Important? Individual bus speed between microprocessor and chipset will increase an order of magnitude in the next 7-10 years. With such high speeds, Copper interconnects on a mother board will be bandwidth-limited due to: – Signal attenuation and distortion (signal-to-noise degradation) – Reflections (signal-to-noise degradation) – Cross-talk and EMI (electromagnetic interference) Optical interconnect achieves higher bandwidth over larger distances than Copper interconnect – Also, components can be spread further apart without impacting Bandwidth, which enables more efficient and cheaper cooling

4 Motivation Optoelectronics (OE) replaced Cu in long (SONET) and short (Enterprise) distances. Extending OE to the computer - Box-to-Box - Board-to-board - Chip-to-chip - On-chip? May allow interconnects to continue to scale in speed However, cost should be acceptable - Comparable or less than electrical IEEE Spectrum, 2002

5 0-2 years2-7 years7+ years Chip-2-Chip (<20”) Brd-2-Brd (<30”, with 2 connectors) Box-2-Box (<3 meters, with 4 connectors & 3 cables) High Speed I/O for Processors – Possible Scenario Copper Optical

6 I/O Architecture Evolution - Optical I/O will be necessary, but hard to predict it’s timing of introduction since Electrical interconnect will continue to innovate SignalingRate(Gb/s) ’s90’s00’s VESA VL EISA MCA PCIx HT HL R I/O AGPx 1Gb/s Parallel Bus 1Gb/s Parallel Bus >12 Gb/s Copper Signaling OpticalInterconnects? Third Generation I/O Architecture Full SerialFull Serial Point to pointPoint to point Max Bandwidth/PinMax Bandwidth/Pin Scalable >10 Gb/sScalable >10 Gb/s FlexibilityFlexibility Multiple market segmentMultiple market segment PCI UP TO 66 Mb/s ISA 8.33 Mb/s

Pentium® CPU Pentium® II CPU Pentium® III CPU Pentium® 4 CPU CPU Platform Bandwidth History (CPU interface and Memory) 8bit DRAM 16bit DRAM 32bit DRAM 32bit DRAM 64bit DRAM EDO 64bit SDRAM PC66/100 64bit SDRAM100/133 64bit DDR bit DDR400  Bandwidth growing exponentially and is expected to continue Bandwidth (MB/sec), CPU Core Freq (MHz) CPU I/F and DRAM BWRDRAM BWCPU Core Freq Optical 20Gb/s per link (40GB/s = 320Gb/s 16 pt-to-pt links)

8 Noise Floor Channel Bandwidth -55 Frequency Line Attenuation (dB) Electrical attenuation Optical attenuation  As Frequency increases, optical interconnect attenuates much more slowly than electrical Optical attenuation Opticzl Conversion Loss Target Data Rate Signal-to-noise increase

9 Summary of Key Points Circuit I/O architecture going from multi-drop bus to a point-to-point bus for performance Chip-to-Chip I/O speed will become limited by the Copper board trace resistance / capacitance (attenuation vs frequency) Beyond ~20Gb/s may need to go to a non-copper board interconnect – Optical waveguide. Chip-to-Chip Optical Interconnect could be introduced when it is faster/better/cheaper than electrical.

10 Summary of Requirements for Optical Interconnect for Chip-to-Chip I/O in Computing Systems Electronic - High-speed (>20Gb/s), low power, CMOS circuits Optical - High-speed (>20Gb/s) Vertical Cavity Lasers (VCSEL) and Photodiodes arrays - Low loss, low cost, optical waveguides (polymer or other) Packaging - Hybrid Integration - Compatible with IC industry - Passive alignment Low cost approach to testing - Compatible with IC industry (in-line testing) - Self-test circuits

11 Key Results for the Optical I/O Technical Paper at Photonics West 1/29/04 Intel researchers built a fully functional chip-to-chip I/O link working at 1-3 Giga-Transfers per second (GT/s). 8 Gb/s aggregate data rate (8 channels each at >1Gb/s) demonstrated chip-to-chip over the optical link. All the optical electronics (driver, receiver amplifier, testing) built in Intel’s low cost 0.18um CMOS All the assembly packaging based upon Intel’s high volume OLGA BGA package Optical elements are 1x12 linear array of GaAs PIN detectors, GaAs Vertical Cavity Lasers (VCSEL), and polymer waveguide. Demonstrated at the system level with a complete functional end-to-end link a highly integrated feasibility prototpye

12 Hybrid Integration Approach Key components - CMOS Transceiver Chip - 1x12 VCSELs, photodetector arrays - 1x12 Polymer waveguide arrays Architecture Advantages: - Parallel architecture increases throughput - Optical port removes distance limitation between two chips - Leverages microprocessor packaging technology Polymer Waveguides VCSELs Transceiver chip Photodiodes MT connector Prototype Waveguide MT connector Photodiodes VCSELs Transceiver chip Schematic of Architecture

13 3Gb/s Transmitter Optical Eye Current System Results Transmitter demonstrated 3Gb/s open eye data transmission. >1Gb/s full-link error-free data transmission obtained. PRBS DATA CLOCK 1Gb/s Full-link Error-Free Transmission PRBS DATA Hybrid Integrated Optical I/O Component Status

14 Summary: Intel has made significant progress demonstrating the feasibility of optical chip-to-chip interconnect. Optical chip-to-chip interconnect may offer a faster, cheaper, better alternative to metal-based data buses between CPU and it’s supporting chips The demonstration was done with 0.18um-CMOS transceiver, with on-chip drivers, amps, and self-test features. The transceiver chip is integrated with the optical emitters, detectors, and wave-guides in a hybrid package This announcement is a progress report from Intel’s Component’s Research Lab. Intel has not made a determination on product plans based upon these results.

15 For further information on Intel's silicon technology, please visit the Silicon Showcase at

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17 Computer I/O Architecture I/O architecture has moved to point to point I/O Bandwidth requirements are likely to exceed more than >10x in next 10 years Optical I/O is consistent with this architectural direction USB2.0 GraphicsGraphics Memory Bridge Memory Bridge PCI Express HDDHDD PCI PCI MemoryMemory CPUCPU SIO Serial ATA Gb Ethernet* Gb Ethernet* Add ins PCI Express I/O Bridge I/O Bridge Add ins LPC

18 Optical IO Architectures Two main approaches based upon levels of Integration – Hybrid/Heterogeneous Component Integration External optical components packaged with the microprocessor – On-Chip Integration Full integration of optical components on logic process flow except CW laser (optical power supply) This research work focuses on the Heterogeneous/Hybrid approach