ATPG - test pattern generation process 1. Target faults 2. Generate test cube: 1-5% 3. Random fill: 99-95% 4. Stimuli on ATE 5. Response on ATE

Scan/ATPG - non-embedded solution ATE stimuli The same width The same frequency ATE reference Mirror images: ATE and scan

ATPG - the bandwidth problem Non-Embedded + Simplicity - Limited number of scan chains - Limited bandwidth Deterministic + High fault coverage + Arbitrary fault models + Minimal number of patterns

Logic BIST Control PRPGMISR 100%100% Fault coverage Logic BIST + test points Logic BIST BIST-ready core requirement  Random pattern testable  X-free responses

Logic BIST Control PRPGMISR Equalizer  Generators Pseudorandom - PRPG Biased Smart Deterministic   Test data eliminated completely   Deigned for board and system test

Logic BIST Embedded - More complex + Unlimited number of scan chains + Short scan load time Pseudorandom + No stored patterns - Lower coverage - More patterns - BIST-ready design

EDT™ - Embedded Deterministic Test  Standard scan  On-chip continuous flow decompressor  On-chip continuous flow selective compactor  Highly compressed deterministic patterns ATEATE Compressed Stimuli Compressed Stimuli Compacted Responses Compacted Responses C CCOMPAOMPACCTORTORCCOMPAOMPACCTORTORCC CCOMPAOMPACCTORTORCCOMPAOMPACCTORTORC DEC DDEECCOMPRESSOROMPRESSORDDEECCOMPRESSOROMPRESSORDEC DDEECCOMPRESSOROMPRESSORDDEECCOMPRESSOROMPRESSOR

Embedded - More complex + Unlimited number of scan chains + Short scan load time Embedded and deterministic test Embedded + Simple + Unlimited number of scan chains + Short scan load time Deterministic + High fault coverage + Arbitrary fault models + Minimal number of patterns

ATPG cycles, coverage, and volume 0% 20% 40% 60% 80% 100% ATPG volume ATPG coverage Cycles

LBIST cycles, coverage, and volume 0% 20% 40% 60% 80% 100% BIST coverage ATPG top-up volume ATPG top-up coverage Cycles

EDT 10X cycles, volume, and energy 0% 20% 40% 60% 80% 100% Cycles ATPG top-up coverage ATPG top-up volume ATPG volume ATPG coverage BIST coverage EDT 10X LBISTLBIST LTPGLTPG ATPGATPG

Radar View of DFT Technologies Reference

ATPGATPGEDTLBISTLTPG

ATPG, Logic BIST ATPGEDTLBISTLTPG

… Logic BIST & ATPG top up patterns ATPGEDTLBISTLTPG

EDT ATPGEDTLBISTLTPG

Logic BIST summary  Logic BIST is ideally suited for applications where stored patterns are prohibitive, i.e. system test  Test coverage objectives are achieved by pseudorandom patterns and test points  Unknown states have to be eliminated to allow signature based compaction  For manufacturing test ATPG top up patterns are required to achieve the desirable test quality  For very long test experiments some un-modeled defects can be detected

EDT summary  EDT is designed for optimized manufacturing test  Based on standard scan No test point are required Handles unknown states  Supports effectively variety of fault models, including path delay faults  Uses tester to execute the test

Deterministic forms of embedded test  Designed for optimized manufacturing test  Tester controls test application  Very similar flow to scan/ATPG Based on standard scan Supports the same fault models as ATPG No test points necessary No bounding of X states necessary (in EDT)  On-chip hardware facilitates the improved efficiency Compression of volume of scan test data Reduction of scan test time

Acknowledgements Alfred Crouch, Motorola Graham Hetherington, Texas Instruments Mark Croft, Mentor Graphics Geir Eide, Teseda Rudy Garcia, NP Test Abu Hassan, Mentor Graphics Mark Kassab, Mentor Graphics Nilanjan Mukherjee, Mentor Graphics Jun Qian, CISCO Nagesh Tamarapalli, Mentor Graphics Robert Thompson, Magma DA Janice Lawson Richards, Mentor Graphics

References and sources  Conference proceedings and tutorial material International Test Conference International Test Conference Design Automation Conference Design Automation Conference Design and Test in Europe Conference Design and Test in Europe Conference VLSI Test Symposium VLSI Test Symposium  Workshops Testing Embedded Core-based Systems Testing Embedded Core-based Systems Memory Technology, Design and Testing Memory Technology, Design and Testing DFT and BIST Workshops DFT and BIST Workshops Test Synthesis Workshop Test Synthesis Workshop

References and sources  Magazines and journals IEEE Design and Test of Computers IEEE Design and Test of Computers IBM Journal of Research and Development IBM Journal of Research and Development ATT Technical Journal ATT Technical Journal IEEE Transactions on CAD of IC&S IEEE Transactions on CAD of IC&S IEEE Transactions on Computers IEEE Transactions on Computers Journal of Electronic Testing (JETTA) Journal of Electronic Testing (JETTA)  Books Abramovici et al., “Digital System Testing and Testable Design”, Computer Science Press, 1990 Abramovici et al., “Digital System Testing and Testable Design”, Computer Science Press, 1990 Bardel et al., “Built-In Test for VLSI”, Wiley, 1987 Bardel et al., “Built-In Test for VLSI”, Wiley, 1987

References and sources  Books Van der Goor, “Testing Semiconductor Memories: Theory and Practice”, John Wiley and Sons, 1991 Van der Goor, “Testing Semiconductor Memories: Theory and Practice”, John Wiley and Sons, 1991 Alfred Crouch, “Design-For-Test for Digital ICs and Embedded Core Systems”, Prentice Hall, 1999 Alfred Crouch, “Design-For-Test for Digital ICs and Embedded Core Systems”, Prentice Hall, 1999 Janusz Rajski and Jerzy Tyszer, “Arithmetic Built-In Self Test for Embedded Systems”, Prentice Hall, 1998 Janusz Rajski and Jerzy Tyszer, “Arithmetic Built-In Self Test for Embedded Systems”, Prentice Hall, 1998  Commercial EDA reference manuals and web pages  ASIC vendors reference manuals and web pages  Patent descriptions and US Patent and Trademark Office web site