Update on Electronics for the SSL 8” Ceramic Detector Matt Andrew, Kurtis Nishimura, Gary S. Varner University of Hawai’i 28-MAR-2012 Discussion 1

Discussion Items These items mainly impact the firmware/software, but having answers would expedite getting 8” ceramic PMT- specific development started 2 1.Self-trigger operation required? 2.Confirm PMT gain (1pC  6x10 6 ) 3.Maximum sustained rate (triggers, occupancy) 4.Multi-hit buffering? 5.How data to be rendered? (online) Yes. 0.5 – few pC (3x10 6 – few x10 7 ) kHz (single hits?) Yes, if possible. Topic for discussion Wednesday (SSL/Berkeley guys to join)

Schedule/Plans On schedule for June integration with 8” ceramic MCP-PMT –Use existing ASICs, boards where possible –Leverage few man-years of development for Belle II Board status 1.Pre-amps in hand, need test (enough boards if design) 2.ASIC daughtercard (will choose IRS2/IRS3 depending on performance [IRS3 in test]) 3.Interface board  in layout (to be submitted in a week or two) 4.SCROD Rev. A in hand; firmware/software exists for readout Integration plan –As components available, send to Berkeley for check –Integration “pow-wow” ~ RT2012 Conference 3

4 Back-up slides

8” Ceramic SSL Ceramic design 5 Conductive epoxy row of GND pins Discrete pig-tail for HV pins

From presentation/discussion in December: 4x boards: (1) amp, (2) DC, (3) Interface, (4) SCROD 6 (2) 8-channel “daughtercards” 9 needed (3)Interface board (wiring, power) 1 needed Power monitoring (1) 4-channel “pre-amps” 18 needed (4) SCROD (Control, Readout) 1 needed

(1) Pre-amp cards: isolation, not just gain 7 Top view: Sample sent to Jason for mechanical check Short ribbon- cable jumpers to reduce strain on pin array Bottom view: Bottom-less socketed pins (slide over signal/ground pins)

(2) Daughtercards (8-ch ASICs underneath) 2x options (plug into same pair 80- pin SMT connector) 8 IRS3 DC (better thermal management) IRS2 DC (better thermal management)

9 (3) Interface board (mostly “just” wiring) Schematics completed, routing started SCROD interface

10 (4) SCROD – small “pre-production run” For details:

Belle II iTOP Readout 8k channels 1k 8-ch. ASICs 64 SRM “board stacks” 64 DAQ fiber transceivers 32 FINESSE 8 COPPER FTSW clock, trigger, programming BLAB waveform sampling ASIC Clock jitter cleaners 64 SRM 8 COPPER 32 DSP FINESSE 9 TRGmod 16 FTSW 64 SRM 11

Readout “board stack” 12 SL10 pulse with TOP electronics prototype (2.7 GSa/s) 12

 Success of PSEC3: proof-of-concept of moving toward smaller feature sizes. Next DRS plans to use 110nm; next SAM plans to use 180 nm. Now a variety of WFS ASIC options… 13