DAQ Map of Electronic Components L. Adeyemi, A. Camsonne, E. Fanchini, JS. Real, R. Suleiman, E. Voutier May 24, 2012.

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Presentation transcript:

DAQ Map of Electronic Components L. Adeyemi, A. Camsonne, E. Fanchini, JS. Real, R. Suleiman, E. Voutier May 24, 2012

VME COMMON CRATE NEW VME 6100 Old TI CAEN V538A TI DB 1 Mott FADC PEPPo (mode 1,2) FADC DB 2 PEPPo (mode 3) FADC S2S1 40MHz clock TDC CAEN V775 Discriminator Caen v985 JLab Discriminator > LNE Delayed From Mott NIM Delay > Helicity From Mott NIM Lin Fan In/Out > PAT Sync From Mott NIM Lin Fan In/Out > GATE From Mott NIM Lin Fan In/Out 740 Mott DetTr from Mott NIM Crate nT_Settle from 794 mod. Mott NIM Lin Fan In/Out 740 Control Channels opsmdaq0 Lemo ECL PEPPo DetTr from CH 4 PEPPo NIM Crate * Lemo 3 ECL TRG IN Common CH 3 PEPPo NIM Crate * OUT TRG (L1A) IN TRG TS#1 TS#2 TRG IN 1 Control Channels Hel., T_Settle, Pat Sync, Pair Sync PMTs from PEPPo Crate Lin Fan In/out PS 740 * Cosmic Det. From Patch Panel Annihilation from PEPPo Crate Lin Fan In/out PS 740 * CH1-CH32 from Mott Crate PS 794 Translator CH1-CH16 from PEPPo Crate PS 794 Translator * 1 – BFM 18 Mott DetTr 19 PEPPo DetTr MJL 7 Gate nT_Settle Mott LT3 Ch16

PEPPo NIM Crate Translator PS 794 Lin Fan In/Out 740 * Lin Fan In/Out 740 * Logic Fan In/Out LeCroy 429A Gate Delayer PS 794 * Pulse Generator Divider Pulse Generator LV Board PMT Bases + 12V Frequency Divider Synch LED A1 A3 P1 P2 P3 P4 P5 P6 P7 P8 P9 PMTs, A1 &A3 => PEPPo FADC mode 1,2 VME Crate PMTs => PEPPo FADC mode 3 VME Crate JLab Discrim VME Crate <= PMTs, A1 & A3 TTL NIM 1 NIM 2 ECL S2 Translator PS 794 Mott Crate PEPPo FADC mode 1,2 Translator PS 794 Mott Crate S1 Discrim. CAEN v895 PEPPo Crate L1A from CAEN V538A MJL from CAEN Discrim Translator PS 794 Mott Crate DB1 VME Crate TRG IN (delayed by 2.0 µs )

Mott NIM Crate BADVtoF 1 MHz 0–10 V LT1 726 VtoF 2 MHz -7 – +7 V LT2 726 LT3 726 LIN 740 DISC 708 QD 794 FAN 429A VtoF 1 MHz 0–10 V → BPM Ch1-16 ← S1 Ch17-32 → BFM -140 mV ← Ch8 FADC ← DISC → BMF -145 MV ← LT3 Ch7 → nT_Settle ← 0.4 µs nT_Settle Trigger → Delayed Helicity → BCM 0L02 Output2 ← VtoF LT3 Ch8 → nT_Settle ← 0.2 µs S1 LNE → T_Settle → 4 MHz Clock ← kHz Clock LT1 Ch4 → Pattern Sync 11 Battery 12 Coil2 → Mott Trigger ← 0.3 µs LT3 Ch9 → Pair Sync 13 Coil3 14 Coil4 15 MPA5D05

Mott NIM – LEVEL TRANSLATOR 726 LT1 NIM INECL OUTNIM OUT 1VtoF S1 Ch1-16 2Scintillator (TS1)/A1 3Mott DetTr50 ΩS2 Ch kHz Clock50 ΩS2 Ch4 5PEPPo DetTr50 ΩS2 Ch5 6LA150 ΩS2 Ch6 7Battery 8PMT1 9PMT2 10PMT3 11PMT4 12PMT5 13PMT6 14PMT7 15PMT8 16PMT9

Mott NIM – LEVEL TRANSLATOR 726 LT2 NIM/ECL INECL OUTNIM OUT 1NIM Delayed Helicity50 ΩFADC2 Ch ECL BatteryLT1 Ch7S2 Ch7 5ECL Coil250 ΩS2 Ch17 6ECL Coil350 ΩS2 Ch18 7ECL Coil450 ΩS2 Ch19 8ECL MPA5D0550 ΩS2 Ch20 9NIM PEPPo DetTrTDC Ch

Mott NIM – LEVEL TRANSLATOR 726 LT3 NIM INTTL/ECL OUTNIM OUT 1Delayed HelicityLT2 Ch1Mott FADC Ch12PEPPo FADC Ch12 2 3T_SettleMott FADC Ch13PEPPo FADC Ch13 4Pattern SyncMott FADC Ch14PEPPo FADC Ch14 5Pair SyncMott FADC Ch15S2 Ch6 6 7BFMTDC Ch17 8VtoFLT1 Ch1S2 Ch1 9Delayed Mott DetTrTDC Ch18 10Mott DetTrCAEN V538A Ch1 11Mott FADC Ch LT1 Ch3QUAD DELAY CH nT_SettleS1 GATE – Ch4PEPPo FADC TRG IN 16nT_SettleQUAD DELAY CH1QUAD DELAY CH2

Mott NIM – QUAD FAN IN/OUT 429A QUAD FAN IN/OUT Delayed Helicity – IN S1 Control – Ch2OUT2 – old Mott DAQOUT1 – old Mott DAQ S2– Ch13LT3 – CH1 T_Settle – IN S2– Ch14LT3 – Ch15FADC2 – Ch12 CAEN V538A – Ch6LT3 – Ch16LT3 – Ch3 Pattern Sync – IN S1 Control – Ch3S2 – Ch15FADC2 – Ch13 LT3 – Ch4 Pair Sync – IN S2 – Ch16FADC2 – Ch14 LT3 – Ch5

CHANNEL ASSIGNMENT – CAEN V538A LEVEL TRANSLATOR ChanIN LEMO PEPPo DetTr 1Mott DetTr 0Delayed (0.4 µs) nT_Settle ChanIN ECL TID OUT TRG (L1A) ChanOUT ECL TID TS#2 1TID TS#1 0TID IN TRG ChanOUT LEMO LA1 (PEPPo NIM)LA1 (TDC COMM) 2 1 0

L1A DELAY Signal to FADC Distribution Board (DB1) TRG IN: I.L1A delayed by 2.0 µs

CHANNEL ASSIGNMENT – TRIGGER INTERFACE (TID) TID ChanIN Signal TS#2 (PEPPo DetTr) 1TS#1 (Mott DetTr) 0TRG (nT_Settle) TID ChanOUT Signal TRG (L1A) 0

Pair -Sync Delayed Helicity T_Settle Pattern-Sync HELICITY SIGNALS

CHANNEL ASSIGNMENT – MOTT FADC Mott Trigger Left E Left ∆E

CONTROL CHANNEL ASSIGNMENT – GATED SCALER S1 S1 CONTROL Chan Signal 1Load-Next-Event (LNE) 2Delayed Helicity 3Pattern Sync 4GATE (nT_Settle) nT_Settle Delayed TID nT_Settle Trigger (Scalers and PEPPo_Int) nT_Settle Trigger Setup: I.nT_Settle Trigger is delayed by 0.4 µs II.LNE is delayed by 0.2 µs nT_Settle LNE

Beat Frequency Modulation (BFM) BFM BFM after -140 mV offset BFM after -145 mV discrimination (TDC) BFM in FADC

NameIncluded ModulesData StorageTrigger ScalersScaler S1 (helicity gated), S2 (ungated) /data/mott/Scalers_%d.datDelayed nT_Settle Mott_SampleMott FADC, S1, S2, TDC/data/mott/Mott_Sample_%d.datMott Detector Mott_SemiIntMott FADC, S1, S2, TDC/data/mott/Mott_SemiInt_%d.datMott Detector Annih_SamplePEPPo FADC, S1, S2, TDC, CAEN VME Discriminator /data/annihilation/Annihilation_Sample_%d.datAnnihilation Detector PEPPo_SamplePEPPo FADC, S1, S2, TDC, 2 VME Discriminators /data/compton/PEPPo_Sample_%d.datCompton Detector PEPPo_SemiPEPPo FADC, S1, S2, TDC, 2 VME Discriminators /data/compton/PEPPo_SemiInt_%d.datCompton Detector PEPPo_IntPEPPo FADC, S1, S2/data/compton/PEPPo_Int_%d.datDelayed nT_Settle Data Taking Modes

HARDWARE OWNERSHIP #CrateDAQ ComponentOwnershipUsers (Mott or PEPPo) Comment 1CAEN VME CrateHall AM&PRack IN02B23 1VMEMVME 6100CISM&Piocmdaq1 1VMECAEN V538A Level TranslatorHall AM&P 1VMETrigger Interface Distribution Board (TID)CISM&P 3VME12-bit ADCCIS1M + 2P 2VMEFADC Distribution BoardCISM&P 2VMESIS3801 ScalerCISM&P 1VMECAEN V895 DiscriminatorLPSCP 1VMECAEN V775 TDCLPSCM&P 1VME40 MHz ClockHall AM&P 1VMEJLab DiscriminatorElectronic GroupP 1NIMVtoF (10 V)Hall AM&P 1NIMVtoF (+/-7 V)CISM&P 1NIMVtoF (single Chan)CISM&P 1NIMDISCRIMINATOR 708CISM 4NIMLINEAR FAN IN/OUT 740CIS +Hall C (3P)1M + 3P 2NIMQUAD DELAY 794CIS1M + 1P 4NIMLEVEL TRANSLATOR 726CIS3M + 1P 2NIMLOGIC FAN IN/OUT 429ACIS1M & 1P 2NIMPulsarLPSC2P 1NIMDividerLPSC1P 1NIMLV Supply BoardLPSC1P 1NIMOctal Login Unit 758CIS1P

Spare Boards #CrateDAQ ComponentOwnershipComment 1VMETrigger Interface Distribution Board (TID)CISOld TI 1NIMLogic Fan In/Out 4282LPSC 1NIMLinear Fan In/Out 428FHall A 1NIMLeCroy Multichannel AnalyzerCIS 2NIMOctal Logic Unit 758CIS

VME Crate

Mott NIM Crate

PEPPo NIM Crate