1 IA-32

TU-Delft TI1400/11-PDS 2 IA family IA (Intel Architecture) is a family of processors Each processor—same architecture, but different organization -same instruction set -different performance 32-bit memory addresses and variable length instructions Very large instruction set (not RISC)

TU-Delft TI1400/11-PDS 3 Floorplan IA-32

TU-Delft TI1400/11-PDS 4 Other Example: PowerPC Floating-point unit Integer unit Instruction unit instructions Cache main memory

TU-Delft TI1400/11-PDS 5 Floorplan PowerPC

TU-Delft TI1400/11-PDS 6 FPU Data Cache Instr. Cache Registers MMU Load/Store Unit Floorplan PowerPC

TU-Delft TI1400/11-PDS 7 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

TU-Delft TI1400/11-PDS 8 IA register structure FP0 FP7 floating - point registers R0 R7 general- purpose registers

TU-Delft TI1400/11-PDS 9 Special registers Code Segment CS Stack Segment SS DS ES FS GS Data Segments

TU-Delft TI1400/11-PDS 10 Status Register OFIF Status Register CFTFSFZF 6789 CFCarry ZFZero SFSign IOPLI/O privilege level OFOverflow IFInterrupt enable IOPL

TU-Delft TI1400/11-PDS 11 Register Naming R0EAX R1EBX R2ECX R3EDX R4 ESP R5 EBP R6 ESI R7 EDI EIP EFLAGS Data registers Pointer registers Index registers Instruction Pointer Status Register

TU-Delft TI1400/11-PDS 12 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

TU-Delft TI1400/11-PDS 13 Memory Memory is byte addressable Doublewords can start at any byte location Data Operands are 8 or 32 bits wide Mode is little-endian scheme (vs big-endian PowerPC)

TU-Delft TI1400/11-PDS 14 Addressable data units byte 3byte 0 310Bit Byte Doubleword 0

TU-Delft TI1400/11-PDS 15 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

TU-Delft TI1400/11-PDS 16 Instructions Variable length instructions 1-12 bytes Five type of instructions -Copy instructions (MOV) -Arithmetic and logic instructions -Flow control -Processor control instructions -I/O instructions Format: INSTR Rdst,Rsrc

TU-Delft TI1400/11-PDS 17 Instruction Format OpcodeAddressingDisplacementImmediate 1 or 2 bytes 1 or 4 bytes variable opcode length

TU-Delft TI1400/11-PDS 18 Addressing modes Many addressing modes: -Immediatevalue -DirectM(value) -Register[reg] -Register IndirectM([reg]) -Base with displacementM([reg]) +Disp -Index with displacementM([reg]  S +Disp) -Base with indexM([reg1]+[reg2]  S) -Base with index and M([reg1]+[reg2]  S+Disp) displacement S=1,2,4 or 8Disp= 8 or 32-bit signed number

TU-Delft TI1400/11-PDS 19 Immediate and Direct Immediate MOV EAX, 25 [EAX]  #25 MOV EAX, 3FA00H [EAX]  # 3FA00H Direct MOV EAX, loc [EAX]  M(loc) or MOV EAX, [loc] [EAX]  M(loc)

TU-Delft TI1400/11-PDS 20 Register indirect Register MOV EBX,OFFSET loc [EBX]  #loc or LEA EBX,loc [EBX]  #loc Register indirect MOV EAX,[EBX] [EAX]  M(EBX)

TU-Delft TI1400/11-PDS 21 Base with Index and Displacement MOV EAX,[EBP+ESI*4+200] EAX  M([EBP] + [ESI]*4 + #200) Operand EBP ESI

TU-Delft TI1400/11-PDS 22 Arithmetic instructions May have one or two operands ADD dst,scr meaning [dst]  [dst] + [src]

TU-Delft TI1400/11-PDS 23 Compare Used to compare values and leave register contents unchanged CMPdst, src[dst] - [src]

TU-Delft TI1400/11-PDS 24 Flow control Two basic branch instructions: JMP[loc]Branch unconditionally JG, JZ, JS, etc Branch if condition is satisfied

TU-Delft TI1400/11-PDS 25 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

TU-Delft TI1400/11-PDS 26 Summation example LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

TU-Delft TI1400/11-PDS 27 Sorting example int[] listarray = new list[n]; int temp; for(j=n-1, j>0, j--){ for(k=j-1, k>=0, k--){ if(list[j] > list[k]) { temp = list[k]; list[k] = list[j]; list[j] = temp; }

TU-Delft TI1400/11-PDS 28 Assembler code LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate

TU-Delft TI1400/11-PDS 29 Question Why is this assembler program an incorrect translation of the Java program?

TU-Delft TI1400/11-PDS 30 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines  really long

TU-Delft TI1400/11-PDS 31 Subroutines CALL sub Return address is saved on stack (ESP register) Return is RET [EIP]  #sub [EIP]  [ESP] [ESP]  [ESP]+4

TU-Delft TI1400/11-PDS 32 Stack instructions ESP register is used as stack pointer PUSH src [ESP]  [ESP] - #4 M([ESP])  [src] POP dst [dst]  M([ESP]) [ESP]  [ESP] + #4 PUSHAD (POPAD) push (pop) all 8 registers on (from) stack

TU-Delft TI1400/11-PDS 33 Stack frames.... PUSH NParameter n on stack 2000CALLSub1Call subroutine at N ESP EIP Note: Sub1 starts at address 2400 Stack Pointer Stack program counter stack pointer

TU-Delft TI1400/11-PDS 34 Subroutine Sub1 Sub1:PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn

TU-Delft TI1400/11-PDS 35 Stack frame in Sub1 [EBX] [EAX] Return Address n ? ESP EIP Stack frame at arrow :PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX Q What is the value op EIP? After PUSH EBX

TU-Delft TI1400/11-PDS 36 Subroutine Sub1 2400PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn After DEC EAX

TU-Delft TI1400/11-PDS 37 Stack frame in Sub1 Stack frame at arrow [EBX] [EAX] Return Address n ? EIP n-1 EAX ESP 2400:PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX After DEC EAX

TU-Delft TI1400/11-PDS 38 Subroutine Sub1 2400:PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn After PUSH EAX

TU-Delft TI1400/11-PDS 39 Stack frame in Sub1 Stack frame at arrow n-1 [EBX] [EAX] Return Address n ? EIP n-1 EAX ESP 2400:PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX.... PUSHEAX After PUSH EAX

TU-Delft TI1400/11-PDS 40 Stack frame in Sub2 Stack frame at arrow Return Address n-1 [EBX] [EAX] Return Address n ? EIP n-2 EAX ESP Sub2:MOVEAX, [EDI+4] DECEAX MOV[EDI+4], EAX RET After DEC EAX

TU-Delft TI1400/11-PDS 41 Stack frame in Sub2 Stack frame at arrow Return Address n-2 [EBX] [EAX] Return Address n ? EIP n-2 EAX ESP Sub2:MOVEAX, [EDI+4] DECEAX MOV[EDI+4], EAX RET After MOV…