Image Compression With Discrete Cosine Transforms Initial Project Proposal – (9/21/99) David Oltmanns Delayne Vaughn John Hill

 Project Objectives  Deliverable  Project Background in Brief  Hardware/Software Component Description  Subsystems Development Decomposition  Timeline  Team Member Responsibilities  Components  Pricing  Special Testing Environments  Hardware, Software Collaborations  References Contents Image Compression With Discrete Cosine Transforms

Our design will use a Connectix QuickCam and PC interfaced to a Xilinx FPGA. We hope to achieve the following goals:  Capture the image using QuickCam  Compress the image using FPGA-based 2-D Discrete Cosine Transform (DCT) on a Xilinx FPGA  Decompress the image using Inverse DCT (IDCT)  Display decompressed image on a PC using a serial port as the interface Project Objectives Image Compression With Discrete Cosine Transforms

Deliverables Our final deliverable will be a compression/decompression system utilizing a FPGA interfaced with a Connectix Quickcam and a PC. The system will allow an image to be captured by the camera, compressed and decompressed by the modules built on the FPGA, and finally returned to the PC. The FPGA will be outfitted with 2-D DCT logic and also incorporate a serial interface, camera interface, and memory control module. Reference figure left. Image Compression With Discrete Cosine Transforms

2-D Discrete Cosine transfer 2-D Inverse Discrete Cosine transfer Project Background in Brief Image Compression With Discrete Cosine Transforms

Project Background in Brief 2-D Fast Discrete Cosine Transform Signal Flow diagram (right) Image Compression With Discrete Cosine Transforms

n Complete System n Compression/Decompression Module(s) n Digital Camera/Camera Interface – (Connectix QuickCam) n SRAM and Memory Control Module n Serial Interface Module for FPGA Hardware/Software Description Image Compression With Discrete Cosine Transforms

 Complete System  Compression/Decompression Module(s)  Digital Camera/Camera Interface  SRAM and Memory Control Module  Serial Interface Module for FPGA Hardware/Software Description Image Compression With Discrete Cosine Transforms

 Complete System  Compression/Decompression Module(s)  Digital Camera/Camera Interface  SRAM and Memory Control Module  Serial Interface Module for FPGA Hardware/Software Description Component location is system (left) Compression, Decompression Module (right) Image Compression With Discrete Cosine Transforms

 Complete System  Compression/Decompression Module(s)  Digital Camera/Camera Interface  SRAM and Memory Control Module  Serial Interface Module for FPGA Hardware/Software Description This figure shows the subset of a previous groups design that interfaces with the camera. We plan on deploying a similar configuration. Image Compression With Discrete Cosine Transforms

 Complete System  Compression/Decompression Module(s)  Digital Camera/Camera Interface  SRAM and Memory Control Module  Serial Interface Module for FPGA Hardware/Software Description Image Compression With Discrete Cosine Transforms

 Complete System  Compression/Decompression Module(s)  Digital Camera/Camera Interface  SRAM and Memory Control Module  Serial Interface Module for FPGA Hardware/Software Description We plan to take existing serial knowledge that has been developed by previous students and integrate it with the rest of our design. One such source is the PDACS project (Spring 1999). Figure 6 shows one scenario that this group used in their project. Image Compression With Discrete Cosine Transforms

Subsystems Development Decomposition n Software Simulation n FPGA Compression n FPGA Decompression n FPGA Module Integration with QuickCam Image Compression With Discrete Cosine Transforms

 Software Simulation  FPGA Compression  FPGA Decompression  FPGA Module Integration with QuickCam Subsystems Development Decomposition Image Compression With Discrete Cosine Transforms

 Software Simulation  FPGA Compression  FPGA Decompression  FPGA Module Integration with QuickCam Subsystems Development Decomposition Image Compression With Discrete Cosine Transforms

 Software Simulation  FPGA Compression  FPGA Decompression  FPGA Module Integration with QuickCam Subsystems Development Decomposition Image Compression With Discrete Cosine Transforms

 Software Simulation  FPGA Compression  FPGA Decompression  FPGA Module Integration with QuickCam Subsystems Development Decomposition Image Compression With Discrete Cosine Transforms

Timeline Week Three Sept Research DCT and sub-systems Begin Proposal Week FourSept Finalize Proposal Present Proposal (Sept. 21) Begin Software Implementation of Compression Algorithm Week FiveSept Oct. 2 Finish Software Compression Algorithm Begin Software Decompression Algorithm Integrate Compression/Decompression Software Components Begin Serial Interface Module Week Six Oct Continue Serial Interface Module Begin SRAM Control Module Biweekly Report 1 (Oct. 7) Week SevenOct Finish Serial Interface Module Finish SRAM Control Module Begin FPGA Compression Module Week EightOct Finish FPGA Compression Module Integrate SRAM, Serial Interface, and Compression Modules Biweekly Report 2 (Oct. 21) Week NineOct Benchmark: Test Integrated FPGA Compression Begin FPGA Decompression Module Begin Camera Interface Begin Mid-term Presentation Week TenOct Nov. 6 Finish FPGA Decompression Module Mid-term Presentation (Nov. 4) Integrate Decompression and Compression Modules Week ElevenNov Finish Camera Interface Integrate Camera Interface with Existing Modules Week TwelveNov Existing Modules Benchmark: Camera Interface with Existing Modules Biweekly Report 3 (Nov. 18) Week ThirteenNov Begin Final Presentation Thanksgiving Week FourteenNov Dec. 3 Overflow (Unforeseen Tasks) Finalize Presentation Week FifteenDec Final Presentation (Dec. 7)

Team Member Responsibilities  Research DCT and sub-systems John, David, Delayne  Prepare ProposalJohn, David, Delayne  Present Proposal (Sept. 21)John, David, Delayne  Software Implementation of Compression AlgorithmDavid, Delayne  Software Implementation of Decompression Algorithm David, Delayne  Integrate Compression/Decompression Software ComponentsDavid, Delayne  Serial Interface ModuleJohn  SRAM Control ModuleJohn  Biweekly Report 1 (Oct. 7)John, David, Delayne  FPGA Compression ModuleJohn, David, Delayne  Integrate SRAM, Serial Interface, and Compression ModulesJohn, David  Biweekly Report 2 (Oct. 21)John, David, Delayne  Benchmark: Test Integrated FPGA Compression John, David  FPGA Decompression ModuleDelayne  Camera InterfaceDavid  Prepare Mid-term PresentationJohn, David, Delayne  Mid-term Presentation (Nov. 4)John, David, Delayne  Integrate FPGA Decompression and Compression ModulesDelayne  Integrate Camera Interface with Existing ModulesJohn, David  Benchmark: Camera Interface with Existing ModulesJohn, David, Delayne  Biweekly Report 3 (Nov. 18)John, David, Delayne  Prepare Final PresentationJohn, David, Delayne  Final Presentation (Dec. 7)John, David, Delayne  Research DCT and sub-systems John, David, Delayne  Prepare ProposalJohn, David, Delayne  Present Proposal (Sept. 21)John, David, Delayne  Software Implementation of Compression AlgorithmDavid, Delayne  Software Implementation of Decompression Algorithm David, Delayne  Integrate Compression/Decompression Software ComponentsDavid, Delayne  Serial Interface ModuleJohn  SRAM Control ModuleJohn  Biweekly Report 1 (Oct. 7)John, David, Delayne  FPGA Compression ModuleJohn, David, Delayne  Integrate SRAM, Serial Interface, and Compression ModulesJohn, David  Biweekly Report 2 (Oct. 21)John, David, Delayne  Benchmark: Test Integrated FPGA Compression John, David  FPGA Decompression ModuleDelayne  Camera InterfaceDavid  Prepare Mid-term PresentationJohn, David, Delayne  Mid-term Presentation (Nov. 4)John, David, Delayne  Integrate FPGA Decompression and Compression ModulesDelayne  Integrate Camera Interface with Existing ModulesJohn, David  Benchmark: Camera Interface with Existing ModulesJohn, David, Delayne  Biweekly Report 3 (Nov. 18)John, David, Delayne  Prepare Final PresentationJohn, David, Delayne  Final Presentation (Dec. 7)John, David, Delayne Image Compression With Discrete Cosine Transforms

Components  Computer  Software including: Xilinx Foundation Series, LabVIEW  FPGA(s)  SRAM  Project Board/Power Supply  Xilinx Interface Cable Pricing  Xilinx XC4010E PC84 FPGA$62.35 (each)  Connectix QuickCam$49.95  WINBOND W24257AX-15 SRAM

Hardware, Software Collaborations HARDWARE SOFTWARE Both hardware and software components are vitally important to the development and implementation of our system. Image Compression With Discrete Cosine Transforms

N. Ahmed, T. Natarajan, and K.R. Rao, "Discrete cosine transform," IEEE Trans. Comput., vol. C-23, pp Jan K. Aldrich, D. Brandenberger, C. Chilek, and B. Raymond, "Sign Language Aquisition and Recognition System," info/cpsc483/common/99b/g3/Final.htm (Sept. 20, 1999) M. Berger, J. Curtin, T. Griffin, A. King, M. Nordfelt, and J. Whitted, "Portable Digital Compression/Decompression System," info/cpsc483/common/99a/g5/g5.html (Sept. 20, 1999) J. Berglund, R. Cuaycong, W. Day, A. Fikes, and K. Shah, "Autonomous Tracking Unit," info/cpsc483/common/99a/g1/g1.html (Sept. 20, 1999) N.I. Cho and S.U. Lee, "Fast algorithm and implementation of 2-D discrete cosine transform," IEEE Trans. CAS, Mar. 1991, pp cosine transform," IEEE Trans. CAS, Mar. 1991, pp N.I. Cho and I.D. Yun, and S.U. Lee, "On the regular structure for the fast 2D DCT algorithm," IEEE Trans. CAS, Apr. 1993, pp S.C. Chan and K.L. Ho, "A new 2D fast cosine transform algorithm," IEEE Trans. SP, Feb. 1991, pp H.S. Hou, "A fast recursive algorithm for computing the discrete cosine transform," IEEE Trans. ASSP, Oct. 1987, pp C.W. Kok, "Fast Algorithm for Computing 2D Discrete Cosine Transform," Unpublished article, pp. 1-4 R. Mahapatra, A. Kumar, and B. Chatterji, "Performance Analysis of 2-D Inverse Fast Cosine Transform Employing Multiprocessors," Article, pp References Image Compression With Discrete Cosine Transforms