1 COMP541 Hierarchical Design & Verilog Montek Singh Jan 28, 2010

Topics  Hierarchical Design  Verilog Primer 2

Design Hierarchy  Just like with large program, to design a large chip need hierarchy  Divide and Conquer To create, test, and also to understand To create, test, and also to understand  Block is equivalent to object 3

Example  9-input odd func (parity for byte)  Block for schematic is box with labels 4

Design Broken Into Modules Use 3-input odd functions 5

Each Module uses XOR 6

Use NAND to Implement XOR  In case there’s no XOR, for example 7

Design Hierarchy 8

9 Components in Design  RHS shows what must be designed

10 Reuse is Common  Certainly forced because of availability of parts (chips)  Also the design cycle was very long  Now more flexibility with programmable logic But still reuse from libraries or intellectual property (IP) But still reuse from libraries or intellectual property (IP) Example: buy a PCI design Example: buy a PCI design Open source, see Open source, see  Note the many logic blocks available in Xilinx library

11 Flow of CAD System Netlist is description of connections Generic Gates Replaces Generic Gates with ones available in Technology Library

12 Technology Mapping  Full custom Pixel-Planes chips (machines in lobby) Pixel-Planes chips (machines in lobby) Memories, CPUs, etc Memories, CPUs, etc  Standard cell Library of cells Library of cells Engineer determined interconnection Engineer determined interconnection  Gate arrays Small circuits with interconnect Small circuits with interconnect

13 Hierarchy Example – 4-bit Equality  Input: 2 vectors A(3:0) and B(3:0)  Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise

14Design  Hierarchical design seems a good approach  One module/bit  Final module for E

15 Design for MX module  Logic function is I’d call this “not E”… I’d call this “not E”… Can implement as Can implement as

16 Design for ME module  Final E is 1 only if all intermediate values are 0  So  And a design is

17 Hierarchical Verilog  We already saw example of instantiation when we used AND and OR gates  Just use module name and an identifier for the particular instance

Vector of Wires (Bus)  Denotes a set of wires input [1:0] S;  Syntax is [a: b] where a is high-order So this could be “[0:1] S” So this could be “[0:1] S” Order will matter when we make assignments with values bigger than one bit Order will matter when we make assignments with values bigger than one bit Or when we connect sets of wires Or when we connect sets of wires  NOTE: THIS IS NOT AN ARRAY! 18

19MX module mx(A, B, E); input A, B; output E; assign E = (~A & B) | (A & ~B); endmodule

20ME module me(E, Ei); input [3:0] Ei; output E; assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]); endmodule

21 Top Level module top(A, B, E); input [3:0] A; input [3:0] B; output E; wire [3:0] Ei; mx m0(A[0], B[0], Ei[0]); mx m1(A[1], B[1], Ei[1]); mx m2(A[2], B[2], Ei[2]); mx m3(A[3], B[3], Ei[3]); me me0(E, Ei); endmodule

22 Integrated Circuit  Known as IC or chip  Silicon containing circuit Later in semester we’ll examine design and construction Later in semester we’ll examine design and construction Maybe processes Maybe processes  Packaged in ceramic or plastic From 4-6 pins to hundreds From 4-6 pins to hundreds  Pins wired to pads on chip

Bonding 23

24 Levels of Integration  SSI Individual gates Individual gates  MSI Things like counters, single-block adders, etc. Things like counters, single-block adders, etc. Like stuff we’ll be doing next Like stuff we’ll be doing next  LSI  VLSI Larger circuits, like the FPGA, Pentium, etc. Larger circuits, like the FPGA, Pentium, etc.

25 Logic Families  RTL, DTL earliest  TTL was used 70s, 80s Still available and used occasionally Still available and used occasionally 7400 series logic, refined over generations 7400 series logic, refined over generations  CMOS Was low speed, low noise Was low speed, low noise Now fast and is most common Now fast and is most common  BiCMOS and GaAs Speed Speed

26Catalogs  Catalog pages describe chips  Look at  Specifications Pinouts Pinouts Packages/Dimensions Packages/Dimensions Electrical characteristics Electrical characteristics

Electrical Characteristics  Fan in max number of inputs to a gate max number of inputs to a gate  Fan out how many standard loads it can drive (load usually 1) how many standard loads it can drive (load usually 1)  Voltage often 1V, 1.2V, 1.5V, 1.8V, 3.3V or 5V are common often 1V, 1.2V, 1.5V, 1.8V, 3.3V or 5V are common  Noise margin how much electrical noise it can tolerate how much electrical noise it can tolerate  Power dissipation how much power chip needs how much power chip needs  TTL high  Some CMOS low (but look at heat sink on a Pentium)  Propagation delay – already talked about it 27

Change Topics to  Verilog First a couple of syntax styles First a couple of syntax styles Help you program more efficiently Help you program more efficiently  Verilog test programs 28

29 Constants in Verilog  Syntax [size][‘radix]constant  Radix can be d, b, h, or o (default d)  Examples assign Y = 10;// Decimal 10 assign Y = ’b10;// Binary 10, decimal 2 assign Y = ’h10;// Hex 10, decimal 16 assign Y = 8’b0100_0011 // Underline ignored  Binary values can be 0, 1, or x

30 Conditional Assignment  Equality test S == 2'b00  Assignment assign Y = (S == 2'b00)? 1’b0: 1’b1; If true, assign 0 to Y If true, assign 0 to Y If false, assign 1 to Y If false, assign 1 to Y

31 4-to-1 Mux Truth Table-ish module mux_4_to_1_dataflow(S, D, Y); input [1:0] S; input [1:0] S; input [3:0] D; input [3:0] D; output Y; output Y; assign Y = (S == 2'b00) ? D[0] : assign Y = (S == 2'b00) ? D[0] : (S == 2'b01) ? D[1] : (S == 2'b01) ? D[1] : (S == 2'b10) ? D[2] : (S == 2'b10) ? D[2] : (S == 2'b11) ? D[3] : 1'bx ; (S == 2'b11) ? D[3] : 1'bx ;endmodule

32 Verilog for Decision Tree module mux_4_to_1_binary_decision(S, D, Y); input [1:0] S; input [1:0] S; input [3:0] D; input [3:0] D; output Y; output Y; assign Y = S[1] ? (S[0] ? D[3] : D[2]) : assign Y = S[1] ? (S[0] ? D[3] : D[2]) : (S[0] ? D[1] : D[0]) ; (S[0] ? D[1] : D[0]) ;endmodule

33 Binary Decisions  If S[1] == 1, branch one way assign Y = S[1] ? (S[0] ? D[3] : D[2]) assign Y = S[1] ? (S[0] ? D[3] : D[2]) and decide Y = either D[2] or D[3] based on S[0] and decide Y = either D[2] or D[3] based on S[0]  Else : (S[0] ? D[1] : D[0]) ; : (S[0] ? D[1] : D[0]) ; decide Y is either D[2] or D[3] based on S[0] decide Y is either D[2] or D[3] based on S[0]  Notice that conditional test is for ‘1’ condition like in C

34 Instance Port Names  Module module modp(output C, input A); module modp(output C, input A);  Ports referenced as modp i_name(conC, conA) modp i_name(conC, conA)  Also as modp i_name(.A(conA),.C(conC)); modp i_name(.A(conA),.C(conC));

35Parameter  Can set constant Like #define Like #define parameter SIZE = 16; parameter SIZE = 16;

36 Verilog for Simulation  Code more convenient than the GUI testbench Also more complex conditions Also more complex conditions Can test for expected result Can test for expected result

37ISE  Make Verilog Test Fixture  Will create a wrapper (a module) Instantiating your circuit Instantiating your circuit It’ll be called UUT (unit under test) It’ll be called UUT (unit under test)  You then add your test code  Example on next slides

38 Module and Instance UUT module syn_adder_for_example_v_tf(); // DATE: 21:22:20 01/25/2004 //...Bunch of comments // Instantiate the UUT syn_adder uut ( syn_adder uut (.B(B),.B(B),.A(A),.A(A),.C0(C0),.C0(C0),.S(S),.S(S),.C4(C4).C4(C4) ); );...endmodule

39Reg  It will create storage for the inputs to the UUT // Inputs reg [3:0] B; reg [3:0] B; reg [3:0] A; reg [3:0] A; reg C0; reg C0;  We’ll talk more about reg next class

40 Wires for Outputs  That specify bus sizes // Outputs wire [3:0] S; wire [3:0] S; wire C4; wire C4;

41Begin/End  Verilog uses begin and end for block  instead of curly braces

42Initial  Initial statement runs when simulation begins initial initialbegin B = 0; B = 0; A = 0; A = 0; C0 = 0; C0 = 0; end end

43 Procedural assignment  Why no “assign”?  Because it’s not a continuous assignment  Explain more next class when we look at storage/clocking

44 Initialize in Default Test File  There’s one in ISE generated file, but don’t think auto_init is defined // Initialize Inputs `ifdef auto_init `ifdef auto_init initial begin initial begin B = 0; B = 0; A = 0; A = 0; C0 = 0; C0 = 0; end end `endif `endif

45 What to Add?  Need to make simulation time pass  Use # command for skipping time  Example (note no semicolon after #50) initial begin begin B = 0; B = 0; #50 B = 1; #50 B = 1; end end

46For  Can use for loop in initial statement block initial begin begin for(i=0; i < 5; i = i + 1) for(i=0; i < 5; i = i + 1) begin begin #50 B = i; end end end

47Integers  Can declare for loop control variables Will not synthesize, as far as I know Will not synthesize, as far as I know integer i; integer j;  Can copy to input regs There may be problems with negative values There may be problems with negative values

48 There are also  While  Repeat  Forever

49Timescale  Need to tell simulator what time scale to use  Place at top of test fixture `timescale 1ns/10ps `timescale 1ns/10ps

50 System Tasks  Tasks for the simulator  $stop – end the simulation  $display – like C printf  $monitor – prints when arguments change (example next)  $time – Provides value of simulated time

51Monitor // set up monitoring initial initialbegin $monitor($time, " A=%b,B=%b\n", A, B); end // These statements conduct the actual test initialbegin Code... Code... end end

Next  Sequential Circuits  We’ll put off the study of arithmetic circuits 52