Lutz Hofmann Fraunhofer ENAS (Germany) 3D Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin MEMS Accelerometer Packages Lutz Hofmann Fraunhofer ENAS (Germany)

OUTLINE Motivation and Objective Selection of TSV approaches Via Last approach: TSV in MEMS-wafer TSV fabrication Demonstrator Via Last approach: TSV in cap-wafer Technology Investigation of silicon direct bonding Conclusion

Integration based on MEMS with TSVs Motivation CMOS Wire Bonds MEMS Conventional MEMS modules Lateral or vertical integration Based on wire bonds Integration based on MEMS with TSVs No wire bonds / bond pad cavities Small size (foot print and height) Short signal paths Direct mechanical contact (nearly) full chip area Improved functionality Driver for Smart Systems (Mobile devices, medical devices, …) CMOS MEMS TSV MEMS CMOS TSV in one device MEMS CMOS TSV in both

Objective - Thin Package Applications Wearable devices, smart cards, …  limited package height Increased functionality: electronics, MEMS, radio, power,... e.g. MEMS accelerometers ( motion detection ) Integration concept : 2.5D integration (Si - interposer) MEMS height < 400 µm  thin 3D-WLP: TSVs, flip chip contact Electronics MEMS Wiring layer Carrier/ Interposer Thin package (~0.8 mm) ~350… 400 µm Example: Smart Card

OUTLINE Motivation and Objective Selection of TSV approaches Via Last approach: TSV in MEMS-wafer TSV fabrication Demonstrator Via Last approach: TSV in cap-wafer Technology Investigation of silicon direct bonding Conclusion

General TSV Technology Approaches Via First TSV MEMS + Cap Thinning & Back end + No temp. limit. for TSV process - Restricted to (Poly)-Si; complete filling - (very) high aspect ratios Via Last + Nearly independent from device-history + (b) Lower AR (for direct bond interface) + Use metals (Cu) for TSVs - Restricted to T < 400…450ºC TSV & Back end processes MEMS + Cap (a: in MEMS) (b: in cap) Via Middle TSV in cap MEMS Bonding & Back end + Decoupled from device + No limitations (temp.) - Bonding: electrical + mech. contact - Bond must withstand further processes AR ... Aspect ratio

Via Last Approaches TSV in MEMS wafer TSV in Cap wafer + Independent from WLB technique (for glass frit, etc.) + Direct interface: hermetic seal + Thinner caps possible + Flexible, nearly any device + Decoupling from MEMS device (TSV isolation) - Ends up with HAR TSVs - Limits of glass frit (sealing, contamination) - Direct bonding required WLB ... Wafer level bonding

OUTLINE Motivation and Objective Selection of TSV approaches Via Last approach: TSV in MEMS-wafer TSV fabrication Demonstrator Via Last approach: TSV in cap-wafer Technology Investigation of silicon direct bonding Conclusion

Via Last – Technology Flow a) Wafer bonding b) Deep Si-etching c) BOX etching d) TSV isolation e) Spacer etching f) ECD: RDL, UBM g) Seed/barrier strip h) Passivation i) Bump formation BOX ... Buried oxide ECD ... Electrochemical deposition RDL ... Redistribution layer UBM ... Under bump metallisation

TSV Etching Processes TSV formation by deep Si etching Using DRIE (BOSCH process) Aspect ratio: 5:1 (50 µm diameter / 250 µm depth) Stop at buried oxide Notching effect due to over-etching (account for non uniformity) Optimisation (partial LF-bias)  reduced effect 50 µm 51 µm 250 µm Glass frit: 9…10 µm 715 nm Reduced notching ~5 µm ~13-23 µm Severe notching TSV profile after optimisation DRIE ... Deep reactive ion etching

TSV Etching Processes BOX etching Contact opening at TSV bottom Dielectric at TSV bottom: 500 nm SiO/SiN Anisotropic RIE process Low pressure, ICP source (Edge of TSV) Al: ~450 nm SiO / SiN (250/250 nm) RIE process for BOX etching Al: ~350 nm (Center of TSV) ICP ... Inductively coupled plasma

TSV Isolation SA-TEOS / O3 SiO2 via SACVD-TEOS process Good step coverage Good adhesion, compatibility Poor dielectric properties Parylene F Good dielectric properties Deposition @ room temp. Post process limited Still under investigation Parylene F 790 nm 402 nm 335 nm (99%) (50%) (42%) 850 nm ( ~85 %) t=230 µm 450 nm ( ~45 %) Nominal values (target thickness): TEOS: 800 nm Parylene: 1000 nm depth: 270 / 230 µm  : 50 µm t=270 µm SACVD ... Sub atmospheric chemical vapour deposition

TSV Etching Processes “Spacer”-etching Re-opening of contact (Al) at TSV bottom Protection of sidewall/surface through non-conformal PECVD SiO2 RIE process with low pressure, and ICP BOX: ~1000 nm SiO2 (SATEOS): ~260 nm Removed SiO2 PE-SiO2 Protection of TSV entrance SATEOS-SiO2 SOI- wafer as test vehicle

TSV Metallisation – Deposition MOCVD TixNy/ Cu: Cu - seed layer TiN - Barrier- / adhesion layer Very high aspect ratios (up to 20:1) Independent from TSV shape: Coverage of negative slopes/undercuts Electrochemical Deposition (ECD) Enhancing seed layer to 5…10 µm Conformal deposition  Reduction of stress (CTE: Cu - Si) process complexity (Process time/ Additive control) (Smearing from sample preparation) TSV: 50x420 µm; 5 µm Cu Conformal deposition even on undercut Undercut (TSV-etching) 1 µm MOCVD ... Metal organic CVD

TSV Metallisation – Pattern Plating Open TSVs  challenge for following processes (patterning, CMP) Residues, particles inside the TSV  Approach: Pattern plating TSV and RDL in one step No subsequent patterning or CMP Open TSVs: 80 x 400 µm; Cu ECD by pattern plating Si wafer TSV Seed-Layer Resist RDL Principle layout for Pattern Plating CMP ... chemical mechanical polishing RDL ... redistribution layer

TSV Metallisation – Plating Mask Dry film resist Easy coverage of cavities Fast/easy lamination, development Lower resolution (~30 µm) !!! Extra equipment required Spin on process Standard litho tools Negative resist (no exposure in TSVs) High viscosity  “tenting” of TSVs Small process window (soft bake)  residues can occur in TSV Seed layer Spin on resist - mask TSV 10 µm SEM image before ECD TSV residues Resist pattern 100 µm Residues of resist in TSVs

Under Bump Metallisation Layers: Cu / Ni / Au – 3-5 µm / 3 µm / 100-500 nm Deposition via pattern plating (same mask as Cu RDL) Critical: selective removal of seed and barrier  High undercut for standard Cu-etchant (up to 10 µm)  Adjusted etchant reduces this effect ( <2 µm) Au 2 µm Ni Cu 2 µm As deposited Standard seed etchant  large undercut After TiN etching  No additional effect Adjusted seed etchant / same TiN etchant

Solder Bumps Deposition via pattern plating (nominal: 40 µm) Using standard SnAg alloy bath (~3% Ag) Reflow at 225ºC, 30”  formation of ball structure SnAg Au-Sn phase 2 µm 2 µm 20 µm 20 µm As deposited After reflow (225ºC)

Demonstrator – MEMS Layout 2-axis MEMS accelerometer based on AIM technology Using existing device not adapted to TSVs TSVs placed at bonding pad area TSV Air gap Metal bridge Moveable element (mass) Spring MEMS 250 µm TSV : 50 µm Cap 400 µm Actual Bond pad Glass frit Principle of AIM Layout Cross section AIM ... Air gap insulated microstructures

Demonstrator – Fabricated MEMS With TSVs Sample prep.: cross sectional polishing (resin embedding) Curvature at TSV-bottom due to porous glass frit layer Spacer etch: TSV area not completely exposed ( SiO2 residues) 200 µm MEMS Cap TSV RDL Glass frit (some pores) 5 µm Cu 50 µm Al Glass frit Liner SiO2 SiO2 residues SEM image after cross sectional polishing Enlarged single TSV

Demonstrator – MEMS After Thinning Thinning cap to 80/82 µm (edge/center) Non uniformity due non optimised stress release etch (RIE) Final thickness: 346 µm (without RDL, bumps) No defects/cracks detectable in cap/MEMS wafer Thinning Cap: 80 µm 200 µm 2 µm 20 µm Cap: 400 µm Device after thinning/dicing

Demonstrator – Functional Test Measured before and after thinning / dicing of MEMS Electrostatic excitation (sinus, Vpp=2 V) Response curve: output current vs. excitation No obvious deviation in both curves  Proof of functionality after final harsh processes

OUTLINE Motivation and Objective Selection of TSV approaches Via Last approach: TSV in MEMS-wafer TSV fabrication Demonstrator Via Last approach: TSV in cap-wafer Technology Investigation of silicon direct bonding Conclusion

Via Last Approach: TSV in Cap wafer Challenges Silicon direct bonding required: low roughness (<1 nm) Not achievable by deposition of bonding SiO2 (e.g. PECVD) Post treatment of MEMS not possible (CMP, wet cleaning, …)  This approach: Pre-preparation of bonding surface Protection of surface during MEMS fabrication

Technology For Direct Bonding And Cap TSV a) Thick PECVD SiO2 b) Planarisation (CMP) c) protective cover film (PCF) d) HARMS fabrication e) Selective PCF removal f) Plasma pre-treatment h) Wafer thinning, TSV fabrication, contact metallisation g) Wafer level bonding

Direct Bonding – Test Vehicle SiO2 bonding frames defined by cavity etching Frame widths: A: 250 µm B: 450 µm C: 650 µm Chip size: 3x3 mm A B C Base wafer: 525 µm Cap: 175 µm Frame Cross section after WLB and thinning Wafer Layout (150 mm)

Direct Bonding – Pre Treatments All cap wafers: wet (SC1) + plasma (O2/N2) Reference wafers: Wet cavity etching before CMP; no protective cover film Reference 1: wet (SC1) + plasma (O2/N2) Reference 2: plasma (O2/N2) MEMS-Dummy: protective cover film used during cavity etching by RIE Pre treatment: plasma (O2/N2) SC1 ... standard clean 1

Direct Bonding – Cavity patterning Critical issues: Defects in protective cover Particles, e.g. resist residues Transfer of defect to bonding surface  Defects Defects Cavity etched Cavity area Final bond surface Particles Protective cover film Patterning of protective cover film (PCF) Cavities etched; PCF removed

Direct Bonding – Bonding Process Hand alignment, no defined pressure Inspection by IR transmission imaging Newton’s rings and darker areas  no bond contact Failure at reference: most likely dishing from CMP Point failures: particles, local damage of bonding surface Wet Reference Dry Reference MEMS-Dummy

Direct Bonding – Annealing Furnace annealing: 400ºC, 5h, N2 No major change in bonding quality Wet Reference Dry Reference MEMS-Dummy

Direct Bonding – Thinning Grinding: Edge trimming (~8 mm) Coarse / fine grinding: 400/100 µm No degradation visible Wet Reference Dry Reference MEMS-Dummy

Direct Bonding – Dicing Dicing: chip raster 3x3 mm² Falling apart of chips with bonding defects Major part unaffected  indirect proof of bonding strength Wet Reference Dry Reference MEMS-Dummy Defective chips

Direct Bonding – Shear Test Reference: blanket chips without frames (i.e. 9 mm² area) No distinct dependency visible Differences most likely due to deviation in frame width (miscalculation of shear strength) Mainly cohesive failure (i.e. Si fracture) Overall: good bonding strength Proof of principle feasibility for “protective cover film” - approach

Conclusion Two Via Last approaches for MEMS TSVs TSV-fabrication demonstrated for MEMS-wafer-TSVs Functional device fabricated with 350 µm final thickness (w/o bumps) Approach based on glass frit: limited in hermiticity, final thickness Approach using cap wafer TSVs: based on silicon direct bonding Method: pre-preparation and protection of bonding surface Test vehicles fabricated with good bonding quality Optimization required: defect free patterning of protection film Further investigations on real MEMS with TSVs are ongoing

Thank you for your attention!