Etron Project: Placement and Routing for Chip-Package-Board Co-Design Progress Report Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering National Taiwan University June 5, 2008 GIEE, NTU

Outline Introduction Problem Formulation Placement and Routing Algorithm

Introduction Cross sections of a die, a BGA package, and a PCB Finger Bonding wire Package wire Die Top metal layer BGA Pin Bump ball Metal layers PCB wire PCB

Chip-Package-Board Co-Design Advantages: Give higher flexibility to design a system Can achieve much higher performance Package planning Determine package size and then place the package on the PCB Package routing Route nets from fingers to bump balls PCB routing Route nets from bump balls to component pins PCB : Fingers : Bump balls Die Component pins Package

Problem of Chip-Package-Board Co-Design Given a die with fingers, a placement of components with pins, the numbers of BGA and PCB metal layers, and a netlist Generate and place the package and then assign signals and route wires from component pins to fingers via bump balls Objectives Maximize routability Minimize package size, total wirelength, and the number of vias PCB : Fingers : Bump balls Die Component pins Package

Example BGA creation and placement BGA and PCB routing

Design Flow Die (Fingers), Components (Pins) # Layers, Netlist, Design Rules Design Flow CPB Placement Bump-Ball Arrangement Package Placement Package and PCB Routing Global Routing Detailed Routing Routing Network Construction Any-Angle Routing No Routed & Minimized? Routing Result Output Yes Layer Assignment

Design Flow Die (Fingers), Components (Pins) # Layers, Netlist, Design Rules Design Flow CPB Placement Bump-Ball Arrangement Package Placement Package and PCB Routing Global Routing Detailed Routing Routing Network Construction Any-Angle Routing No Routed & Minimized? Routing Result Output Yes Layer Assignment

Bump-Ball Arrangement Determine package size (can get the minimum rectangle size) # bump balls of (r-1) rings < # fingers < # bump balls of r rings Bump ball ring r-1 ring r Fingers

Package Placement (1/2) Pin yboundary xboundary Apply linear programming (LP) to determine the location of the package Step 1: Define legal regions of package placement Pin 3 4 yboundary q (x1, y1) 1 Package Center c (xc, yc) x=0 (x2, y2) 2 (xp, yp) p r y=0 xboundary

Package Placement (2/2) Step 2: Formulate LP Objective function: Minimize total wirelength Min |(xc+xp)-x1|+|(yc+yp)-y1|+|(xc+xp)-x2|+|(yc+yp)-y2|+ |(xc+xp)-x3|+|(yc+yp)-y3|+|(xc+xp)-x4|+|(yc+yp)-y4| Subject to Package placement in legal regions xp>xboundary yp+package width<yboundary xp>0 yp>0 Min A A≧|(xc+xp)-x1| (A≧(xc+xp)-x1; A≦-(xc+xp)+x1)

Design Flow Die (Fingers), Components (Pins) # Layers, Netlist, Design Rules Design Flow CPB Placement Bump-Ball Arrangement Package Placement Package and PCB Routing Global Routing Detailed Routing Routing Network Construction Any-Angle Routing No Routed & Minimized? Routing Result Output Yes Layer Assignment

Global Routing (1/3) Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball Apply network flow to do global routing Multi-sources Single sink Use s2 to choose the bump pads for Type 1 s2 b1 b4 Netlist: 1, 2, 3 es1_1 1 b na f1 b2 b5 s1 Ball t a f2 2 Pin c f3 Finger b3 b6 Pre-assigned signals Only given a netlist PCB BGA Chip

Global Routing (2/3) Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball Apply network flow to do global routing Multi-sources Single sink s2 b1 b4 Netlist: 1, 2, 3 1 g f1 b2 b5 s1 t f2 2 Pin h f3 Finger b3 b6 Only given a netlist PCB BGA Chip

Global Routing (3/3) Apply LP to solve the routing network LP formulation: Objective function & constraints Objective function: Minimize total wirelength min Σl(ei_j)ei_j (l(ei_j): length of ei_j) Subject to Capacity of each edge/node (model routing resource) ei_j ≦ cap(ei_j); ni ≦ cap(ni); Flow constraint Σei_j = Σej_k Routability constraint es1_i = 1 Σes2_bi = # fingers – Σes1_j

Global Routing Result 1 Netlist: 1, 2, 3 1 3 2 2 Pre-assigned Signals Ball 3 2 Pin 2 Finger 2 Pre-assigned Signals Only given a netlist PCB BGA Chip

Layer Assignment (1/2) In global routing, integrate all metal layers into one layer Model the layer assignment as a flow network to distribute nets into each layer after global routing Can only route 2 wires in one layer 1 1 e1_l Layer 1 es_1 l el_t 1 3 3 Ball s t 3 2 r es_2 er_t 2 2 Finger e2_r Layer 2 BGA Chip Flow network

Layer Assignment (2/2) Apply LP to solve the flow network Objective function: Minimize total via cost min Σci_jei_j (ci_j: via cost of ei_j) Subject to Capacity of each metal layer el_t ≦ 2; er_t ≦ 2 Flow constraint es_1 = 1; es_2 = 1; es_3 = 1 Σei_j = Σej_k Whole net in the same metal layer A net is composed of two wires p and q ei_lp = ei_lq; ei_rp = ei_rq BGA PCB

Detailed Routing The PCB routing does not allow any routing path with an acute angle The router should check every turning point to avoid an acute angle Once an acute corner is detected, the two adjacent net segments can be cut off to generate two obtuse angles Acute angle Turn Original routing path Min. spacing ring : Pins : Bump balls

Differential Pair Implement the proposed algorithm Consider differential pairs Can have better signal integrity Differential pair

Preliminary Layout

Schedule Problem of Chip-Package-Board Co-Design Stage 1 (1/2008 – 4/2008): done Literature survey Development of a placement and routing algorithm considering the objectives Stage 2 (5/2008 – 7/2008): almost done Implementation of the placement and routing algorithm Stage 3 (8/2008 – 9/2008) Optimization of the objectives Stage 4 (10/2008 – 12/2008) GUI generation and integration of all functions Paper writing and documentation