Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

Workshop 5 – Data Types A Nets Registers Register Data Types Examples Vectors Indexed part select Concatenation and Replication Exercise 5

Nets Net: Data type used to model physical connection between structural elements. Net has a value continuously driven by: - Continuous assignment - module or gate instantiation The most commonly used net is declared with Keyword “wire”. Its default value is Z. wire Y will continuously assume value at the output of AND gate. Net is a one bit value (scalar) by default unless it is declared vector (array of bits) explicitly. A B Y Net is not a keyword - it is a class of data types. wire Y ; // declaration assign Y = A & B ;

Registers Registers are abstractions of storage devices found in real system. Register retains its value until it is overridden, within procedural blocks. Register types (keywords): reg ,integer, real, time reg: any size, unsigned (can be declared as signed), default size is 1, default value is X integer: 32-bit signed variable (2’s complement) real: 64-bit, real number, decimal or scientific notations, default value 0, no range declaration time: 64-bit, unsigned. Defaults to initial value of 0 integer, real are similar to C programming. Verilog register is not the same as a hardware register – no need for driver or a clock. Integers used for counting

Register Data Types Examples reg OK_flag ; // 1-bit register reg [31:0] data1 ; // 32bits, Little Endian notation reg [0:31] data2 ; // 32bits, Big Endian notation integer counter ; // 32-bit. initial counter = -1 ; real delta ; // delta = 2.13 ; delta = 4e10 ; time save_sim_time ; /* System function $time is invoked to get the current simulation time */ save_sim_time = $time ; We will use the Little Endian notation

Vectors Vector : “net” or “reg” data types can be declared as vectors (multiple bit widths). If bit width is not specified the default is 1 bit (scalar). Example: wire [7:0] a ; reg [31:0] b ; reg c ; Both bit-select and part-select can be used. Examples: reg [11:0] counter ; reg a ; reg [2:0] b ; a = counter[7] ; // bit seven is loaded into a b = counter[4:2] ; // bits 4, 3, and 2 are loaded into b Vector - multiple-bit data. Scaler - single-bit data.

index part select Verilog permits variable bit selects of vector and indexing vectors, using variable expressions, to perform dynamic parts select (use a variable to select a specific byte out of a word. The syntax is as follows: [base_expression +: width_expression] or [base_expression -: width_expression] base_expression can be a variable expression, vary during simulation run-time but width_expression must be a constant Offset direction indicates if the width_expression is added (+:) or subtracted (-:) from the base_expression. In Verilog1995, variable bit selects of vector are permitted, but part-selects must be constant. It is illegal to use variable to select a specific byte out of word

index part select examples reg [31:0] a ; b = a[8+:16] ; // b = a[23:8] c = a[31-:8] ; // c = a[31-24] reg [63:0] word ; reg [3:0] byte_num ; //a value from 0 to 7. reg [7:0] byteN ; byteN = word[byte_num*8 +: 8] ; // If byte_num = 4, byteN = word[39:32] parameter outwidth = 8 ; // output data width reg [4:0] position = 0 ; // input data bit position output reg [outwidth:0] dout ; // output data dout = din[position-:outwidth] ;

indexed part select example // Break down a 40-bit vector string into 5 separate bytes Use 5 bytes hard-coded slices Use indexed part select module indexarr ; reg [39:0] str ; // string initial begin str = "abcde“ ; $display("%s", str[7:0]) ; $display("%s", str[15:8]) ; $display("%s", str[23:16]) ; $display("%s", str[31:24]) ; $display("%s", str[39:32]) ; end endmodule // output: e, d, c, b, a module indexarr ; reg [39:0] str ; // string integer i ; initial begin str = "abcde“ ; for (i = 0 ; i < 5 ; i = i + 1) $display("%s", str[i*8 +: 8]) ; end endmodule

Concatenation and Replication The concatenation operator { } provides mechanism to append multiple operands. Operands must be sized. Examples: A = 1’b1 ; B = 2’b00 ; C = 2’b10 ; D = 3’b110 ; Y = {B, C} ; // Result Y is 4’b0010 Y = {A, B, C, D, 3’b001} ; // Result Y is 11’b10010110001 Y = {A, B[0], C[1]} ; // Result Y is 3’b101 assign {b [7:0], b[15:8]} = {a[15:8], a [7:0]} ; // Byte swap assign FA_out = {cout, sum} ; // Full Adder output: carry out + Sum Repetitive concatenation of the same number, can be expressed by using the replication constant. Y = {4{A}} ; // Result Y is 4’b1111 Y = {4{A}, 2{B}, C} ; // Result Y is 10’b1111000010

Concatenation and Replication MIPS Add immediate Instruction. Instruction syntax: addi $t,$s,C. Opcode: 816 . Meaning: $t = $s + C (signed). Used to add sign-extended constants. C Exercise: Extend the 16bit immediate 2’C value to 32bit word Input [31:0] inst ; // Instruction input reg [31:0] sign_ext ; // Extended 2’C Constant to ALU Answer: sign_ext = {16{inst[15]}, inst[15:0]} ; // Keep 2’C Cont. sign Extra: Extend the 16bit immediate logic value to 32bit word to execute andi and ori immediate instructions (16msbs = 0) Answer: sign_ext = {16{1’b0}, inst[15:0]} ;

n-bit Signals Multi-bit buses and signals are easily defined in Verilog. Example: 2-to-1 multiplexer with 8-bits operands module mux 2_to_1 (a, b, sel, out) ; input [7:0] a, b ; input sel ; output reg [7:0] out ; always @(a, b, sel) begin if (sel) out = a ; else out = b ; end endmodule 1 out 8 sel a b MUX Can be easily implemented using continuous assignment: assign out = (sel)? A : b ;

Exercise 5 Answer: sign_ext = {16{1’b0}, inst[15:0]} ; Index Part Select reg [255:0] buffer ; reg [7:0] byteN ; reg [31:0] wordN ; parameter byte_num = 5 ; parameter word_num = 7 ; 1. Write expression for byteN and its value in buffer bits 2. Write expression for wordN and its value in buffer bits Answers: 1. byteN = buffer[byte_num*8 +: 8] ; // buffer[47:40] 2. wordN = buffer[(word_num*32-1) -: 32] ; //buffer[223:192] Concatenation and Replication Extend the 16bit immediate logic value within the MIPS instruction, to 32bit word, in order to execute andi and ori immediate instructions (16msbs = 0) Parametric Bus Driver-Receiver Answer: sign_ext = {16{1’b0}, inst[15:0]} ;