FPGA Implementation of Linear Model Predictive Controller for Closed Loop Control of Intravenous Anesthesia Guide:- Prof. D. N. Sonawane By:- Prashant Basargi ( )

Objectives Understanding Linear MPC and QP problem Active-set method Hardware/Software Co-Simulation Testing of developed MPC architecture for closed loop control of intravenous anesthesia Simulation of various clinical trials

Model Predictive Control: Block Diagram MPC strategy

Types of Model Predictive Control:

Tuning parameters of MPC: 1.Sample time 2.Prediction horizon 3.Control horizon

Methods to solve QP problems : 1.Active set method 2.Interior point method 3.Gradient Projection method

Why Active Set ? Best suitable for less numbers of variables Gives more exact solutions and sensitivity information for less number of variables Active set methods are more stable than interior-point methods for less numbers of variables

Hildreth Algorithm: 1.Find initial values of X – Find H -1 matrix – Cholesky decomposition [L and L T ] – Inverting triangular matrix [L -1 and (L T ) -1 ] – Multiplication of L -1 and (L T ) -1 – Multiplication of H -1, C and -1 2.Find optimum values of λ P=M x H -1 x M T – Multiplication of M and H -1 – Multiplication of above calculated matrix and M T

Continued… 3. d = (M x H -1 x C) + K – multiplication of M, H-1 and C – Addition of above calculated matrix and K matrix 4. Using lower triangular matrix of P calculate the values of λ 1 1, λ 2 1, λ Using matrix P and above calculated values of λ find values of λ 1 2, λ 2 2, λ Using this optimum value of λ calculate optimum value of X * by, X * = X - H -1 x M T x λ * – Multiplication of H-1, MT and λ* – Subtract above calculated value from initial value of X.

Cholesky decomposition A = L * L Algorithm: 1.Determine l11 and L21 2.Compute L22 from

Synthesis report: Device Utilization Summary (estimated values)[-] Logic UtilizationUsedAvailableUtilization Number of Slice Registers % Number of Slice LUTs % Number of fully used LUT-FF pairs % Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166% Number of DSP48A1s85813% MATLAB Execution time= sec= nsec FPGA Clock cycle required=24 Execution time=120 nsec

Hildreth Algorithm: synthesis report MATLAB Execution time= sec = microsec FPGA Clock cycle required=224 Execution time=1.12 microsec Device Utilization Summary (estimated values)[-] Logic UtilizationUsedAvailableUtilization Number of Slice Registers % Number of Slice LUTs % Number of fully used LUT-FF pairs % Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166% Number of DSP48A1s85813%

Fix to float synthesis report: Results: Input numberExpected outputProposed IP core output ’h40AAE ’hC1391EB ’h3CBC6A7F32’h3CBC6A40 Device Utilization Summary (estimated values) Logic UtilizationUsedAvailableUtilization Number of Slice Registers % Number of Slice LUTs % Number of fully used LUT-FF pairs % Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166%

Addition/Subtraction Synthesis report: Results: Input number1Input number2Expected output Addition/subtraction Proposed IP core output Addition/subtraction 32’h ’h40AAE14832’h417D70A4/ 32’h40A51EB8 32’h417D70A0/ 32’h40A51EB8 32’h405AE14832’hC1391EB832’hC / 32’h416FD70A 32’hC / 32’h416FD70A Device Utilization Summary (estimated values)[-] Logic UtilizationUsedAvailableUtilization Number of Slice Registers % Number of Slice LUTs % Number of fully used LUT-FF pairs % Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166%

Multiplication Synthesis report: Results: Device Utilization Summary (estimated values) Logic UtilizationUsedAvailableUtilization Number of Slice LUTs % Number of fully used LUT-FF pairs 0540% Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166% Number of DSP48A1s4586% Input number1Input number2Expected output Multiplication Proposed IP core output Multiplication 32’h ’h40AAE14832’h426047AE32’h 32’h405AE14832’hC1391EB832’hCC21E471132’h

Division Synthesis report: Results: Device Utilization Summary (estimated values) Logic UtilizationUsedAvailableUtilization Number of Slice LUTs % Number of fully used LUT- FF pairs % Number of bonded IOBs % Number of BUFG/BUFGCTRLs 1166% Input number1 Input number2Expected output Division Proposed IP core output Division 32’h ’h40AAE14832’h3FFBAF7632’h 32’h405AE14832’hC1391EB832’h3E9757D732’h

Square root synthesis report: Results: Input numberExpected output Square root Proposed IP core output Square root ’h4013E4DE ’h4059B1B ’h3E1B4C1B Device Utilization Summary (estimated values)[-] Logic UtilizationUsedAvailableUtilization Number of Slice LUTs % Number of fully used LUT-FF pairs 09000% Number of bonded IOBs % Number of BUFG/BUFGCTRLs1166%

Objective completed: Different IP cores : o IEEE 754 Floating Point Number Converter and Arithmetic units o Matrix algebra o Cholesky Decomposition o Active set method

Objective to be completed: Hardware/Software Co-Simulation Testing of developed MPC architecture for closed loop control of intravenous anesthesia. Simulation of various clinical trials

Literature Survey E. Furutani and Y. Sawaguchi, “A hypnosis control system using a model predictive controller with online identification of individual parameters”, Proceedings of the 2005 IEEE Conference on Control Applications Toronto, Canada, August 28-31, 2005, N. Cardoso and J.M. Lemos, “Model Predictive Control of depth of Anesthesia: Guidelines for controller configuration”, 30 th annual international IEEE EMBS conference vancouver, british columbia, canada, August 20-24, D. Ingole, D. N. Sonawane, V. Naik, D.Ginoya, V. Patki, “Implementation of Model Predictive Control for Closed Loop Control of Anesthesia”, proceeding of the third International Conference on control, communication and power engineering (CCPE-2012),Bangalore, India: Springer-Verlag,2012, pp

Fix to float conversion:

Addition/subtraction :

Multiplication:

Division: