晶片系統設計流程與工具 SoC Design Flow & Tools 熊博安 (Pao-Ann Hsiung) 國立中正大學資訊工程研究所 (National Chung Cheng University, CSIE) EA-204 (05) ext Office: EA-512

What will you learn from this course? What is a System-on-Chip (SoC)? –Motivation –History –State-of-Art What are the design issues? –Complexity: digital, analog, mixed, IP, memory, … –Hardware-software codesign –Functional Verification: full-chip, hw, sw, … How to design and verify an SoC? –Design & Verification Flow –Design & Verification Tools

Who should take this course? Interested in becoming a system (hardware- software) engineer Interested in designing SoCs EE background: learn system design, embedded software design, verification CS background: learn SoC architecture, embedded hardware design, verification Essential backgrounds: C/C++ programming, computer architecture, OS

Who should NOT take this course? Only wants course credits Only because SoC is popular Does not like research Does not like projects Does not like using tools or lab work Not creative (lack of new ideas) Yawns and goes to sleep when someone is talking about system design

Reference Books (Design) Daniel D. Gajski et al., “ Specification and Design of Embedded Systems, ” Prentice Hall, Henry Chang et al., “ Surviving the SoC Revolution, ” Kluwer Academic Publishers, Bassam Tabbara et al., “ Function/Architecture Optimization and Co- Design of Embedded Systems, ” Kluwer Academic Publishers, Michael Keating, Pierre Bricaud, “ Reuse Methodology Manual, ” Kluwer Academic Publishers, Frank Vahid, Tony Givargis, “ Embedded System Design, ” John Wiley & Sons, Inc., Steve Furber, “ ARM System-on-Chip Architecture, ” 2nd Edition, Addison Wesley, 2000.

Reference Books (Verification) Prakash Rashinkar, Peter Paterson, Leena Singh, “ System-on-a-chip Verification, ” Kluwer Academic Publishers, Lionel Bening, Harry Foster, “ Principles of Verifiable RTL Design, ” Kluwer Academic Publishers, 2001.

Course Syllabus & Schedule TopicWeek Introduction 1 System Modeling2 ~ 4 Hardware-Software Codesign5 ~ 7 Mid-Term8 SoC Verification9 ~ 10 Configurable Processors11 SoC Testing12 ~ 13 Project Presentations14 Final Exam15

Course Grading Mid-Term Exam30% Final Exam30% Digital Camera Project16% 6 Labs24%

Digital Camera Project Design a digital camera SoC with hardware and software (JPEG) Schedule –Written ReportMay 31, 2005 –PresentationMay 31, 2005 –DemonstrationBefore Final Exam Grade: (total 16%) –Report 5%, Presentation 5%, Demo 6%

SIX Labs Familiarity with Tools 1.Cadence SystemC/Verilog/VHDL simulators 2.UML Editor and Simulator 3.Mentor Seamless Co-Verification Environment (CVE) 4.FPGA design tools Altera Quartus II v3.0, SoPC Builder Xilinx ISE Foundation, and other tools 5.Coware ConvergenSC 6.Tensilica Xtensa Configurable Processor

Labs All 6 labs (total 24%) –Assignmentlast ½ hour –Deadlineafter 2 weeks –Gradingfaster  higher grades –Demonstrationcontact TA –TA = 邱冠綸, Ext , Lab EA305

SoC Design Flow & Tools ENJOY THE COURSE!!!