Comparison of various TSV technology ELEC 5070 Term paper SONG Wenjie

Outline · What is Through Silicon Via(TSV) · Advantages of TSV · Various TSV Technology

Outline · What is Through Silicon Via(TSV) · Advantages of TSV · Various TSV Technology

· What is Through Silicon Via(TSV) High integration technology → Small, high speed, multi-functional devices This miniaturization is technologically → (limited by)the leak current → generates heat & signal delay in circuit → (caused by) wiring 3D packaging technology are expected to make a breakthrough in such miniaturization on 2D surface → (enable)high density integration by stacking LSI chips → with smaller footprint → save the space that would be necessary for bonding wires → improve packaging density

Outline · What is Through Silicon Via(TSV) · Advantages of TSV · Various TSV Technology

·Advantages of TSV 1) Small size and high density Can be used for the perpendicular construction of LSIs in a 3D space, and require a footprint at a fraction of that of a conventional LSI Can potentially be used effectively for stacking processor cores in a CPU composed of multi cores to realize a highly parallel processor LSI 2) High speed signal propagation and processing Reduce the total wiring length Higher speeds in signal propagation and a reduction of signal delays Increase the design flexibility 3) Low power consumption Electrical resistance causes heating, enables the elimination of such heating Reducing the number of repeaters(save power) 4) Many input-output terminals Wire bondings are located at the edges of an LSI chip, whereas , TSV place input-output terminals in arbitrary positions in an LSI chip

Outline · What is Through Silicon Via(TSV) · Advantages of TSV · Various TSV Technology

·Various TSV Technology Characterization & Reliability Via exposure RDL(Re-distribution layer) μ- Bump Post-TSV Process TSV Fabrication TSV Assembly TSV enabling technologies Via first/last High AR via Thin wafer handling Design, Test, Characterization & Reliability Stacking C2C,C2W bonding Fine gap underfill

·Various TSV Technology Process Flow: TSV Fabrication Via first/last High AR via Thin wafer handling

·Various TSV Technology TSV Fabrication Vertical via - is suitable for finer pitch (<100µm). The interconnection will be partial metal disposition (lining) or solid metal filling. Lining has less thermomechanical stress (Si CTE is ~3ppm/K but Cu CTE is 20ppm/k) and an easy process compared to solid via, but emptiness of the via will cause reliability issues. Tapered via - is suitable for lower I/O Count device, with larger pitch (> 150 um). It is used for power amplifier (PA) backside ground applications and CMOS TSV image sensors. Via first/last High AR via Thin wafer handling

·Various TSV Technology Via-First Process The dimensions are typically smaller (5–20 μm wide), with aspect ratios of 3:1 to 10:1. TSV Fabrication Via-First : interfere with device layer Via-Last : interfere with both device and metal layers Via first/last High AR via Thin wafer handling Via-Last Process The dimensions are wider (20–50 μm), with aspect ratios of 3:1 to 15:1.

·Various TSV Technology Techniques for forming high aspect ratio deep silicon via structures: Bosch etch process cryogenic etch process laser drilling powder blast micromachining TSV Fabrication Via first/last High AR via Thin wafer handling

·Various TSV Technology Bosch etch process: TSV Fabrication C4F8 → passivation Fluorine radicals(in SF6 )→removing passivation layer of the base of the trench SF6 → etch the exposed silicon at bottom Via first/last High AR via Thin wafer handling Pro: Very high aspect-ratio (>60:1) sub-micron Con: A characteristic sidewall ripple of 100–200 nm

·Various TSV Technology Cryogenic etch process: TSV Fabrication Perform two steps simultaneously using SF6 and O2 gases SiOXFY on the sidewalls (@T≈-100 °C) → passivation Via first/last High AR via Thin wafer handling Pro: low sidewall roughness (a few nanometers) Con: fast etch rate (passivation and etching proceed concurrently)

·Various TSV Technology Laser drilling process: TSV Fabrication Via first/last High AR via Thin wafer handling Pro: significant low cost due to lithography free Con: heat from lasers lead to low reliability and stress gradient

·Various TSV Technology Powder blast micromachining: TSV Fabrication Via first/last High AR via Thin wafer handling A particle jet is directed toward the target material Cyclone ventilate particles → 80-200 m/s

·Various TSV Technology Thin (~50μm) wafer handling: UV curable epoxy/glass bonding – Using glass wafer as supporting, dispensed UV curable epoxy to bonding and debonding Polymer adhesive – Using high temperature polymer materials to meet process temperature needs and debond from support wafers @ 200~250°C Electrostatic bonding – Using electrostatic bonding, wafer can be temporary attached to electrostatic chuck for several hours. TSV Fabrication Via first/last High AR via Thin wafer handling

·Various TSV Technology The main challenges : smooth via sidewalls uniform deposition of dielectric isolation layer over the via sidewall continuity of copper diffusion barrier and copper seed metallization void-free copper electroplating. TSV Fabrication Via first/last High AR via Thin wafer handling

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